AT89C5122D-RDRUM datasheet(136/208 Pages) ATMEL

136 / 208 page

136

AT83R5122, AT8xC5122/23

4202F–SCR–07/2008

Slave Select (SS)

Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay

low for any message for a Slave. Only one Master (SS high level) can drive the network.

The Master may select each Slave device by software through port pins (Figure 82). To

prevent bus conflicts on the MISO line, only one slave should be selected at a time by

the Master for a transmission.

In a Master configuration, the SS line can be used in conjunction with the MODF flag in

the SPI Status register (SPSTA) to prevent multiple masters from driving MOSI and

SCK (see Section “Error Conditions”, page 140).

A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.

The SS pin could be used as a general-purpose if the following conditions are met:

•

The device is configured as a Master and the SSDIS control bit in SPCON is set.

This kind of configuration can be found when only one Master is driving the network

and there is no way that the SS pin will be pulled low. Therefore, the MODF flag in

the SPSTA will never be set (1).

•

The Device is configured as a Slave with CPHA and SSDIS control bits set (2). This

kind of configuration can happen when the system comprises one Master and one

Slave only. Therefore, the device should always be selected and there is no reason

that the Master uses the SS pin to select the communicating Slave device.

Baud Rate

In Master mode, the baud rate can be selected from a baud rate generator which is con-

troled by three bits in the SPCON register: SPR2, SPR1 and SPR0. The Master clock is

chosen from one of six clock rates resulting from the division of the internal clock by 4, 8,

16, 32, 64 or 128.

Table 83 gives the different clock rates selected by SPR2:SPR1:SPR0

Table 83.

SPI Master Baud Rate Selection

Clearing SSDIS control bit does not clear MODF.

Special care should be taken not to set SSDIS control bit when CPHA = ’0’ because in

this mode, the SS is used to start the transmission.

SPR2:SPR1:SPR0

Clock Rate

Baud Rate Divisor (BD)

000

Reserved

N/A

001

FCK_SPI /4

010

FCK_SPI / 8

011

FCK_SPI /16

100

FCK_SPI /32

101

FCK_SPI /64

110

FCK_SPI /128

128

111

Reserved

N/A

AT89C5122D-RDRUM 数据表(PDF) 136 Page - ATMEL Corporation

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