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XIO2000AI 数据表(PDF) 104 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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XIO2000AI 数据表(HTML) 104 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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104 / 159 page  Classic PCI Configuration Space 94 April 2007 Revised October 2008 SCPS155C Table 4−47. Serial IRQ Edge Control Register Description (Continued) BIT FIELD NAME ACCESS DESCRIPTION 1† IRQ1_MODE RW IRQ 1 edge mode 0 = Edge mode (default) 1 = Level mode 0† IRQ0_MODE RW IRQ 0 edge mode 0 = Edge mode (default) 1 = Level mode † These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset. 4.74 Serial IRQ Status Register This register indicates when a level mode IRQ is signaled on the serial IRQ stream. After a level mode IRQ is signaled, a write-back of 1b to the asserted IRQ status bit re-arms the interrupt. IRQ interrupts that are defined as edge mode in the serial IRQ edge control register are not reported in this status register. See Table 4−48 for a complete description of the register contents. PCI register offset: E4h Register type: Read/Clear Default value: 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4−48. Serial IRQ Status Register Description BIT FIELD NAME ACCESS DESCRIPTION 15 IRQ15 RCU IRQ 15 asserted. This bit indicates that the IRQ15 has been asserted. 0 = Deasserted 1 = Asserted 14 IRQ14 RCU IRQ 14 asserted. This bit indicates that the IRQ14 has been asserted. 0 = Deasserted 1 = Asserted 13 IRQ13 RCU IRQ 13 asserted. This bit indicates that the IRQ13 has been asserted. 0 = Deasserted 1 = Asserted 12 IRQ12 RCU IRQ 12 asserted. This bit indicates that the IRQ12 has been asserted. 0 = Deasserted 1 = Asserted 11 IRQ11 RCU IRQ 11 asserted. This bit indicates that the IRQ11 has been asserted. 0 = Deasserted 1 = Asserted 10 IRQ10 RCU IRQ 10 asserted. This bit indicates that the IRQ10 has been asserted. 0 = Deasserted 1 = Asserted 9 IRQ9 RCU IRQ 9 asserted. This bit indicates that the IRQ9 has been asserted. 0 = Deasserted 1 = Asserted 8 IRQ8 RCU IRQ 8 asserted. This bit indicates that the IRQ8 has been asserted. 0 = Deasserted 1 = Asserted 7 IRQ7 RCU IRQ 7 asserted. This bit indicates that the IRQ7 has been asserted. 0 = Deasserted 1 = Asserted |
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