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XIO2000AI 数据表(PDF) 106 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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XIO2000AI 数据表(HTML) 106 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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106 / 159 page  PCI Express Extended Configuration Space 96 April 2007 Revised October 2008 SCPS155C 5 PCI Express Extended Configuration Space The programming model of the PCI Express extended configuration space is compliant to the PCI Express Base Specification and the PCI Express to PCI/PCI-X Bridge Specification programming models. The PCI Express extended configuration map uses the PCI Express advanced error reporting capability and PCI Express virtual channel (VC) capability headers. All bits marked with a k are sticky bits and are reset by a global reset (GRST) or the internally-generated power-on reset. All bits marked with a † are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset. The remaining register bits are reset by a PCI Express hot reset, PERST, GRST, or the internally-generated power-on reset. Table 5−1. PCI Express Extended Configuration Register Map REGISTER NAME OFFSET Next capability offset / capability version PCI Express advanced error reporting capabilities ID 100h Uncorrectable error status register† 104h Uncorrectable error mask register† 108h Uncorrectable error severity register† 10Ch Correctable error status register† 110h Correctable error mask† 114h Advanced error capabilities and control† 118h Header log register† 11Ch Header log register† 120h Header log register† 124h Header log register† 128h Secondary uncorrectable error status† 12Ch Secondary uncorrectable error mask† 130h Secondary uncorrectable error severity register† 134h Secondary error capabilities and control register† 138h Secondary header log register† 13Ch Secondary header log register† 140h Secondary header log register† 144h Secondary header log register† 148h Reserved 14Ch Next capability offset / capability version PCI express virtual channel extended capabilities ID 150h Port VC capability register 1 154h Port VC capability register 2 158h Port VC status register Port VC control register 15Ch VC resource capability register (VC0) 160h VC resource control register (VC0) 164h VC resource status register (VC0) Reserved 168h VC resource capability register (VC1) 16Ch VC resource control register (VC1) 170h VC resource status register (VC1) Reserved 174h Reserved 178h – 17Ch VC arbitration table (phase 7 − phase 0) 180h VC arbitration table (phase 15 − phase 8) 184h VC arbitration table (phase 23 − phase 16) 188h † These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset. |
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