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XIO2000AI 数据表(PDF) 110 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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XIO2000AI 数据表(HTML) 110 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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110 / 159 page  PCI Express Extended Configuration Space 100 April 2007 Revised October 2008 SCPS155C 5.5 Uncorrectable Error Severity Register The uncorrectable error severity register controls the reporting of individual errors as ERR_FATAL or ERR_NONFATAL. When a bit is set, the corresponding error condition is identified as fatal. When a bit is cleared, the corresponding error condition is identified as nonfatal. See Table 5−4 for a complete description of the register contents. PCI Express extended register offset: 10Ch Register type: Read-only, Read/Write Default value: 0006 2011h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 Table 5−4. Uncorrectable Error Severity Register Description BIT FIELD NAME ACCESS DESCRIPTION 31:21 RSVD R Reserved. Returns 000 0000 0000b when read. 20† UR_ERROR_SEVR RW Unsupported request error severity 0 = Error condition is signaled using ERR_NONFATAL (default) 1 = Error condition is signaled using ERR_FATAL 19† ECRC_ERROR_SEVR RW Extended CRC error severity 0 = Error condition is signaled using ERR_NONFATAL (default) 1 = Error condition is signaled using ERR_FATAL 18† MAL_TLP_SEVR RW Malformed TLP severity 0 = Error condition is signaled using ERR_NONFATAL 1 = Error condition is signaled using ERR_FATAL (default) 17† RX_OVERFLOW_SEVR RW Receiver overflow severity 0 = Error condition is signaled using ERR_NONFATAL 1 = Error condition is signaled using ERR_FATAL (default) 16† UNXP_CPL_SEVR RW Unexpected completion severity 0 = Error condition is signaled using ERR_NONFATAL (default) 1 = Error condition is signaled using ERR_FATAL 15† CPL_ABORT_SEVR RW Completer abort severity 0 = Error condition is signaled using ERR_NONFATAL (default) 1 = Error condition is signaled using ERR_FATAL 14† CPL_TIMEOUT_SEVR RW Completion time-out severity 0 = Error condition is signaled using ERR_NONFATAL (default) 1 = Error condition is signaled using ERR_FATAL 13† FC_ERROR_SEVR RW Flow control error severity 0 = Error condition is signaled using ERR_NONFATAL 1 = Error condition is signaled using ERR_FATAL (default) 12† PSN_TLP_SEVR RW Poisoned TLP severity 0 = Error condition is signaled using ERR_NONFATAL (default) 1 = Error condition is signaled using ERR_FATAL 11:5 RSVD R Reserved. Returns 000 0000b when read. 4† DLL_ERROR_SEVR RW Data link protocol error severity 0 = Error condition is signaled using ERR_NONFATAL 1 = Error condition is signaled using ERR_FATAL (default) 3:1 RSVD R Reserved. Return 000b when read. 0 RSVD R Reserved. Returns 1b when read. † These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset. |
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