H5GQ1H24AFR-R0C datasheet(7/173 Pages) HYNIX

7 / 173 page

Rev. 1.0/Nov. 2009

H5GQ1H24AFR

0.1. DEFINITION OF SIGNAL STATE TERMINOLOGY

GDDR5 SGRAM will be operated in both ODT Enable (terminated) and ODT Disable (unterminated)

modes. For highest data rates it is recommended to operate in the ODT Enable mode. ODT Disable mode

is designed to reduce power and may operate at reduced data rates. There exist situations where ODT

Enable mode can not be guaranteed for a short period of time, i.e. during power up.

Following are four terminologies defined for the state of a device (GDDR5 SGRAM or controller) pin dur‐

ing operation. The state of the bus will be determined by the combination of the device pins connected to

the bus in the system. For example in GDDR5 it is possible for the SGRAM pin to be tristated while the

controller pin is High or ODT. In both cases the bus would be High if the ODT is enabled. For details on

the GDDR5 SGRAM pins and their function see “PACKAGE SPECIFICATION” on page 156 and “SIG‐

NALS” on page 158 in the section entitled “PACKAGE SPECIFICATION” on page 156.

Device pin signal level:

•High: A device pin is driving the Logic “1” state.

•Low: A device pin is driving the Logic “0” state.

•Hi‐Z: A device pin is tristate.

•ODT: A device pin terminates with ODT setting, which could be terminating or tristate depending on Mode

Bus signal level:

•High: One device on bus is High and all other devices on bus are either ODT or Hi‐Z. The voltage level on the bus

would be nominally VDDQ

•Low: One device on bus is Low and all other devices on bus are either ODT or Hi‐Z. The voltage level on the bus

would be nominally VOL(DC) if ODT was enabled, or VSSQ if Hi‐Z.

•Hi‐Z: All devices on bus are Hi‐Z. The voltage level on bus is undefined as the bus is floating.

•ODT: At least one device on bus is ODT and all others are Hi‐Z. The voltage level on the bus would be nominally

VDDQ.

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