H5GQ1H24AFR-R0C datasheet(94/173 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.0 /Nov. 2009

H5GQ1H24AFR

Figure 61. READ to PRECHARGE

DBI

n+7

Bank a,

Col n

CK#

DBI#

CL = CLmrs = 6

WCK#

WCK

T7n

T6n

tRTP

Bank a,

or all

DONʹT CARE

TRANSITIONING DATA

tRP

2. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.

4. tRTP = tRTPL when bank groups are enabled and the PRECHARGE command accesses the same bank; otherwise tRTP = tRTPS.

5. Before the READ commands, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDRD must be met.

1. CLmrs = 6 is shown as an example. Actual supported values will be found in the MR and AC timings sections.

3. EDC may be on or off. See Figure 4 for EDC Timing.

Notes:

6. tWCK2DQO = 0 is shown for illustration purposes.

NOP

READ

PRE

NOP

ADDRESS

COMMAND

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