H5GQ1H24AFR-R0C datasheet(46/173 Pages) HYNIX

46 / 173 page

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.0 /Nov. 2009

H5GQ1H24AFR

value of 120 Ohms is equivalent to the 40 Ohms Pulldown and 60 Ohms Pullup nominal impedances of

GDDR5 SGRAMs. RESET#, CK and CK# are not internally terminated. CK and CK# shall be terminated on

the system using external 1% resistors to VDDQ.

The output driver and on‐die termination impedances are updated during all REFRESH commands to

compensate for variations in supply voltage and temperature. The impedance updates are transparent to

the system.

Driver Strength

Bits A0 and A1 define the driver strength. The Auto Calibration setting enables the Auto‐Calibration

functionality for the Pulldown, Pullup and Termination over process, temperature and voltage changes.

The design target for the factory setting is 40 Ohm Pulldown, 60 Ohm Pullup driver strength with nominal

process, voltage and temperature conditions.

The nominal option enables the factory setting for the Pulldown, Pullup driver strength and termination.

With this option enabled, driver strength and termination are expected to change with process, voltage

and temperature. AC timings are only guaranteed with Auto Calibration.

Data Termination

Bits A2 and A3 define the data termination value for the on‐die termination (ODT) for the DQ and DBI#

pins in combination with the driver strength setting.

The termination can be set to a value of ZQ/2 which is intended for a single loaded system, or ZQ which

is intended for a weaker termination used in a lower power or frequency applications. The data

termination may also be turned off.

ADR/CMD Termination

Bits A4 and A5 define the address/command termination. The default setting (’00’) provides that the

address/command termination is determined by latching CKE# on the rising edge of RESET#.

The address/command termination can also be set to a value of ZQ/2 which is intended for a single

loaded system, or ZQ which is intended for double loaded configurations with two devices sharing a

common address/command bus. The address/command termination may also be turned off.

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