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H5GQ1H24AFR-R0C 数据表(PDF) 11 Page - Hynix Semiconductor

部件名 H5GQ1H24AFR-R0C
功能描述  1Gb (32Mx32) GDDR5 SGRAM
PDF  173 Pages
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制造商  HYNIX [Hynix Semiconductor]
网页  http://www.skhynix.com/kor/main.do
标志 HYNIX - Hynix Semiconductor

H5GQ1H24AFR-R0C 数据表(HTML) 11 Page - Hynix Semiconductor

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009
11
H5GQ1H24AFR
Figure 3: GDDR5 SGRAM Power‐up Initialization
1.2. Initialization with Stable Power
The following sequence is required for reset subsequent to power‐up initialization. This requires that the 
power has been stable within the specified VDD and VDDQ ranges since power‐up initialization (See 
Figure 4)
Table 1  Address and Command Termination
VALUE (OHMS)
CKE# at RESET# high transition
ZQ/2
Low
ZQ
High
TRAIN / MRS
TRAIN / MRS
ADR
CKE#
min. 200 μs
CMD
VDD
VDDQ
VREFD/C
RESET#
tATS tATH
Voltages and
CK stable
DQ<31:0>,
DBI#<3:0>
ADR
EDC<3,0>
All Banks
Precharge
WCK
NOP
NOP
CK#
CK
WCK#
PRE
NOP
tRP
Execution of steps
13‐21 in Power‐up
sequence
TRAIN / MRS
TRAIN / MRS
ADR
A.C.
ADR ADR
min. 200 μs
NOP
NOP
EDC<2,1>
x32
x16
TRAIN / MRS
A.C.
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Note:  A.C. = Any Command



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