H5GQ1H24AFR-R0C datasheet(35/173 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.0 /Nov. 2009

H5GQ1H24AFR

Figure 18: LDFF Command Address to DQ/DBI#/EDC Mapping

All burst addresses 0 to 7 must be loaded; LDFF commands to burst address 0 to 6 may be issued in ran‐

dom order; the LDFF command to burst address 7 (LDFF7) must be the last of 8 consecutive LDFF com‐

mands, as it effectively loads the data into the FIFO and results in a FIFO pointer increment. Consecutive

LDFF commands have to be spaced by at least tLTLTR, and at least tLTL7TR cycles are required after each

LDFF command to burst address 7.

LDFF pattern may efficiently be replicated to the next FIFO stages by issuing consecutive LDFF commands

to burst address 7 (with identical data pattern). The data pattern in the scratch memory for LDFF will be

available until the first RDTR command.

The DQ/DBI# output buffers remain in ODT state during LDFF.

An amount of LDFF commands to burst address 7 greater than the FIFO depth is allowed and shall result

in a looping of the FIFO’s data input.

The total number of LDFF commands to burst address 7 modulo FIFO depth must equal the total number

of RDTR commands modulo FIFO depth when used in conjunction with RDTR. No READ or WRITE com‐

mands are allowed between LDFF and RDTR.

The EDC hold pattern is driven on the EDC pins during LDFF (provided RDQS mode is not enabled).

A10

A11

BA1

1 FIFO STAGE = 1 BURST

Burst Position

BA2

BA1

BA0

LDFF FIFO Load Pulse

LDFF Command

CK#

Address‐to‐DQ Mapping

BA3

DBI0# DBI1# DBI2# DBI3#

EDC0 EDC1 EDC2 EDC3

DQ7

DQ15 DQ23 DQ31

DQ6

DQ14 DQ22 DQ30

DQ5

DQ13 DQ21 DQ29

DQ4

DQ12 DQ20 DQ28

DQ3

DQ11 DQ19 DQ27

DQ2

DQ10 DQ18 DQ26

DQ1

DQ9

DQ17 DQ25

DQ0

DQ8

DQ16 DQ24

Byte 0Byte 1Byte 2 Byte 3

BA0

BA2

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