 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
H5GQ1H24AFR-R0C 数据表(PDF) 8 Page - Hynix Semiconductor |
|
|
|||||||||||||||||||||||||||||
H5GQ1H24AFR-R0C 数据表(HTML) 8 Page - Hynix Semiconductor |
|
|
8 / 173 page  This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 8 H5GQ1H24AFR 0.2. CLOCKING The GDDR5 SGRAM operates from a differential clock CK and CK#. Commands are registered at every rising edge of CK. Addresses are registered at every rising edge of CK and every rising edge of CK#. GDDR5 uses a DDR data interface and an 8n‐prefetch architecture. The data interface uses two differen‐ tial forwarded clocks (WCK/WCK#). DDR means that the data is registered at every rising edge of WCK and rising edge of WCK#. WCK and WCK# are continuously running and operate at twice the frequency of the command/address clock (CK/CK#). Figure 1: GDDR5 Clocking and Interface Relationship CK CK# COMMAND ADDRESS DQ*1 WCK WCK# Note : Figure.1 shows the relationship between the data rate of the buses and the clocks and is not a timing diagram. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
