H5GQ1H24AFR-R0C datasheet(40/173 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.0 /Nov. 2009

H5GQ1H24AFR

Data from any WRTR burst may be concatenated with data from a subsequent WRTR command. A contin‐

uous flow of data can be maintained. The first data element from the new burst follows the last element of

a completed burst. The new WRTR command should be issued after the previous WRTR command

according to the tCCDS timing.

A RDTR can be issued any time after a WRTR command as long as the internal bus turn around time

tRTWTR is met.

The total number of WRTR commands modulo FIFO depth must equal the total number of RDTR com‐

mands modulo FIFO depth when used in conjunction with RDTR. No READ or WRITE commands are

allowed between WRTR and RDTR.

Figure 21: Write Training using WRTR and RDTR Commands

CK#

CMD

WLmrs

NOP

WRTR

1. WLmrs, CLmrs and CRCRL set to 1 for ease of illustration; check Mode Register definition for supported settings

WRTR

ADDR

Ta+1

Ta+2

Ta+3

Ta+4

NOP

RDTR

NOP

RDTR

NOP

WCK

WCK#

EDC

EDC Hold

Donʹt Care

WLmrs

CLmrs

CRCRL

CLmrs

CRCRL

tWTRTR

2. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.

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