H5GQ1H24AFR-R0C datasheet(43/173 Pages) HYNIX

43 / 173 page

Rev. 1.0 /Nov. 2009

H5GQ1H24AFR

WRITE Latency (WLmrs)

The WRITE latency (WLmrs) is the delay in clock cycles used in the calculation of the total WRITE latency

(WL) between the registration of a WRITE command and the availability of the first piece of input data.

DRAM vendor specifications should be checked for value(s) of WLmrs supported. The full WRITE latency

definition can be found in the section entitled OPERATION.

When the WRITE latencies are set to small values (i.e. 1,2,... clocks), the input receivers never turn off, in

turn, raising the operating power. When the WRITE latency is set to higher values (i.e. .. 6, 7 clocks) the input

receivers turn on when the WRITE command is registered. Refer to vendor datasheets for value(s) of

WLmrs where the input receivers are always on or only turn on when the WRITE command is registered

Speed

Allowable Operating Frequency (Gbps)

WL7

WL6

WL5

WL4

WL3

WL2

WL1

6.0Gbps

5.5Gbps

5.0Gbps

4.5Gbps

4.0Gbps

CAS Latency (CLmrs)

The CAS latency (CLmrs) is the delay in clock cycles used in the calculation of the total READ latency

(CL) between the registration of a READ command and the availability of the first piece of output data.

By default CLmrs is specified by bits A3‐A6, defining a CLmrs range of 5 to 20 tCK.

DRAM vendor specifications should be checked for value(s) of CLmrs supported. The full READ latency

definition can be found in the section entitled OPERATION

Speed

RDBI

ON/OFF

Allowable Operating Frequency (Gbps)

CL20

CL19

CL18

CL17

CL16

CL15

CL14

CL13

CL12

6.0Gbps

OFF

5.5Gbps

OFF

5.0Gbps

OFF

4.5Gbps

OFF

4.0Gbps

OFF

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