H5GQ1H24AFR-R0C datasheet(72/173 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.0 /Nov. 2009

H5GQ1H24AFR

Figure 43. WRITE Timings

CK#

tCH

tCL

tCK

WLmrs

DQ/DBI#

(mean)

WCK#

WCK

tWCK2CKPIN + tWCK2CK

tWCK2DQI

DQ/DBI#

(first bit)

DQ/DBI#

(last bit)

tDQDQI(min)

tDQDQI(max)

1) WLmrs is the WRITE latency programmed in Mode Register MR0.

2) Timings are shown with positive tWCK2CKPIN and tWCK2CK values. See WCK2CK timings for

tWCK2CKPIN and tWCK2CK ranges.

3) tWCK2DQI parameter values could be negative or positive numbers, depending on PLL‐on or PLL‐off mode

operation and design implementation. They also vary across PVT. Data training is required to determine

the actual tWCK2DQI value for stable WRITE operation.

4) tDQDQI defines the minimum to maximum variation of tWCK2DQI within a double byte (x32 mode) or

a single byte (x16 mode).

5) Data Read timings are used for CRC return timing from WRITE commands with CRC enabled.

D1 D2 D3 D4 D5 D6 D7

Case 1: Negative tWCK2DQI

DQ/DBI#

(mean)

tWCK2DQI

DQ/DBI#

(first bit)

DQ/DBI#

(last bit)

tDQDQI(min)

tDQDQI(max)

D1 D2 D3 D4 D5 D6 D7

Case 2: Positive tWCK2DQI

Donʹt Care

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