H5GQ1H24AFR-R0C datasheet(28/173 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.0 /Nov. 2009

H5GQ1H24AFR

After exiting WCK2CK training mode, the WCK phase is allowed to further drift from the ideal alignment

point by a maximum of tWCK2CK (e.g. due to voltage and temperature variation). Once this WCK phase

drift exceeds tWCK2CK(min) or tWCK2CK(max), it is required to repeat the WCK2CK training and realign

the clocks.

WCK2CK alignment at PIN Mode

The WCK and CK phase alignment point can be changed via MRS by setting bit A0 in MR6. In normal

mode, when MR6 A0 is set to ‘0’, the phases of CK and WCK are aligned at CK pins and the end of WCK

tree as shown in Figure 13. On the other hand, when MR6 A0 is set to ‘1’, the phases of CK and WCK are

aligned at the pin as shown in Figure 14. PIN mode is supported up to the max CK clock frequency of

fCKPIN, and is an option to reduce the time of WCK2CK training at low frequency.

Figure 13: Normal Mode

Figure 14: Pin Mode

WCK2CK Auto Synchronization

GDDR5 SGRAMs support a WCK2CK automatic synchronization mode that eliminates the need for

WCK2CK training upon power‐down exit. This mode is controlled by the autosync bit (MR7, bit A4), and

is effective when the LP2 bit (MR5, bit A1) is set and the WCK clocks are stopped during power‐down.

CK#

WCK

WCK#

EDC

Internal WCK/2

Internal CK

Phase

Detector

CK#

WCK

WCK#

EDC

Internal WCK/2

Internal CK

Phase

Detector

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