H5GQ1H24AFR-R0C datasheet(39/173 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.0 /Nov. 2009

H5GQ1H24AFR

WRTR Command

A WRTR burst is initiated with a WRTR command as shown in Figure 20. No bank or column addresses

are used as the data is written to the internal READ FIFO, not the array. The length of the burst initiated

with a WRTR command is eight. There is no interruption nor truncation of WRTR bursts.

Figure 20: WRTR Command

A WRTR command may only be issued when a bank is open or a refresh is in progress and bit A2 in MR5

is set to 0 to allow training during refresh.

WDBI and WRCRC must be enabled to write the DBI and EDC bits, respectively, with the WRTR com‐

mand. If WDBI is not set, a ‘1’ will be written to the DBI FIFO, and a ‘1’ will be assumed for the DBI# input

in the CRC calculation. In contrast to a normal WRITE, no CRC is returned by the WRTR command and

the EDC pins will drive the EDC hold pattern.

In case of the RDQS mode, the EDC pin functions like with a normal READ in this mode. Please note that

RDCRC must be enabled to read the calculated CRC data with the RDTR command.

An amount of WRTR commands equal to the FIFO depth is required to fully load the FIFO; any number of

WRTR commands greater than the FIFO depth is allowed and shall result in a looping of the FIFO’s data

input. The FIFO depth to which the WRTR data is written must be 6. The FIFO depth is read via the Ven‐

dor ID function.

During WRTR bursts, the first valid data‐in element must be available at the input latch after the Write

Latency (WL). The Write Latency is the same as for WRITE.

Upon completion of a burst, assuming no other WRTR data is expected on the bus the GDDR5 SGRAM

DQ and DBI# pins will be driven according to the ODT state. Any additional input data will be ignored.

WRTR

CS#

WE#

CAS#

RAS#

CKE#

LOW

CK#

A9 (A12)

A8,A10,A11

BA0‐BA3

A2‐A5

0,1,1

A7,A0,A6

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