H5GQ1H24AFR-R0C datasheet(23/173 Pages) HYNIX

23 / 173 page

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.0 /Nov. 2009

H5GQ1H24AFR

Figure 9: Address Training Timing

Table 10 defines the correspondence between address bits and DQ/DBI#. Devices configured to x16 mode

reflect the address on the two bytes being enabled in that mode, which are bytes 0 and 2 for MF=0 and

bytes 1 and 3 for MF=1 configurations. Devices configured to x32 mode reflect the address on the same DQ

as in x16 mode; in addition they are allowed but not required to reflect the address on those bytes that are

disabled in x16 mode, thus reflecting each address twice.

Devices not supporting an A12/RFU pin shall drive a logic High on the DBI# pins.

Table 9 AC timings in Address Training Mode

Parameter

Symbol

Min

Max

Unit

READ command to data out delay

tADR

0.5*tCK+0

0.5*tCK+10

ADT off to DQ/DBI# in ODT state delay

tADZ

‐‐

0.5*tCK+10

CK#

tADR

Even

Notes:

1) READ command encoding: CS# = L, RAS# = H, CAS# = L, WE# = H

2) ADRxR = 1st half of address x, sampled on rising edge of CK;

ADRxR# = 2nd half of address x, sampled on rising edge of CK#

3) Addresses sampled on rising edge of CK are returned on even DQ after tADR;

addresses sampled on rising edge of CK# are returned on odd DQ simultaneously with even DQ

4) DQs are enabled when ADT bit in Mode Register 15 set to 1 (Enter Address Training Mode)

DQs are disabled after tADZ when ADT bit in Mode Register 15 set to 0 (Exit Address Training Mode)

ADRx

CMD

ADDR

ADRy

Odd

tADR

tMRD

MR15

A10=1

ADRx

Donʹt Care

ADRx

ADRy

ADRx

ADRy

ADRz

tADR

MR15

A10=0

tADZ

ADRz

MRS

NOP

READ (*)

NOP

READ (*)

NOP

READ (*)

NOP

MRS

NOP

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