H5GQ1H24AFR-R0C datasheet(100/173 Pages) HYNIX

100 / 173 page

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.0 /Nov. 2009

100

H5GQ1H24AFR

Figure 67. EDC Calculation matrix

The CRC calculation is embedded into the WRITE and READ data stream as shown in Figure 16:

•for WRITEs, the CRC checksum is calculated on the DQ and DBI# input data before decoding with DBI

•for READs, the CRC checksum is calculated on the DQ and DBI# output data after encoding with DBI

The bit ordering is optimized for errors in the time burst direction. Figure 67 shows the bit orientation on a

byte lane basis. All ʹ1sʹ are assumed in the calculation for the DBI# in burst in case DBI is disabled for

WRITEs or READs in the Mode Register.

The CRC calculation is also not affected by any data mask sent along with WDM, WDMA, WSM or WSMA

commands.

The EDC latency is based on the CAS latency for READ data and the WRITE latency for WRITE data.

Table 25 shows the 2 timing parameters associated with the EDC scheme.

Mode Register 4 is used to determine the functionality of the EDC pin. Register bits A9 and A10 control the

GDDR5 SGRAM’s CRC calculation independently for READs and WRITEs. With EDC off, the calculated

CRC pattern will be replaced by the EDC hold pattern defined in Mode Register bits A0 ‐ A3. See “Mode

Registers on page 39” section for more details.

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DBI0#

Burst 8 Ordering (2 tCK)

CRC Data Input

DQ/DBI# bit ordering

CRC Polynomial

T0 + 8 U.I.

CRC Data Output

EDC bit ordering

Burst 8 Ordering (2 tCK)

X0 X1 X2 X3 X4 X5 X6 X7

T0 + 8 U.I.

X8 + X2 + X + 1 = 0 x 83 = ( X + 1) (X7 + X6 + X5 + X4 + X3 + X2 + 1)

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