H5GQ1H24AFR-R0C datasheet(107/173 Pages) HYNIX

107 / 173 page

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.0 /Nov. 2009

107

H5GQ1H24AFR

Figure 72. SELF REFRESH Entry Command

Figure 73. Self Refresh Entry and Exit

Note:

1. Clock(CK and CK#) must be stable before exiting self refresh mode.

2. Device must be in the all banks idle state prior to entering self refresh mode.

3. tXSNRW is required before any non‐READ or WRITE command can be applied, and tXSRW is required before a READ or WRITE command can be

applied.

4. REF = REFRESH command.

CS#

WE#

CAS#

RAS#

CKE#

A9‐A11 (A12)

A0,A1,A6

BA0‐BA3

A2‐A5

HIGH

Self‐Refresh

CK#

CMD

SRE

NOP

ADDR

Ta0

Tb2

Tb0

Tb1

Td0

SRX

PREA

Valid

NOP

tCPDED

CKE#

NOP

tCKSRE

tCKSRX

tRP

Tc0

Enter Self Refresh Mode

Exit Self Refresh Mode

tXSNRW

tXSRW

tRDSRE or tWRSRE

Self refresh exit requires WCK2CK training prior to any WRITE or READ operation

At least one REFRESH command shall be issued after tXSNRW for output driver and termination impedance updates.

NOP

Donʹt Care

tCMDS

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