H5GQ1H24AFR-R0C datasheet(159/173 Pages) HYNIX

部件名	H5GQ1H24AFR-R0C

功能描述	1Gb (32Mx32) GDDR5 SGRAM

PDF	173 Pages

Scroll/Zoom	100%

制造商	HYNIX [Hynix Semiconductor]

网页	http://www.skhynix.com/kor/main.do

标志

159 / 173 page

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.0 /Nov. 2009

159

H5GQ1H24AFR

Figure clarifies the use of the MF=0 and MF=1 ball‐outs in x16 mode and why the bytes are renumbered to

give the controller the view of the same bytes that a controller sees with a single x32 device. This is impor‐

tant for Address Training, DM and EDC functionality. For more details see the x16 enable and MF enable

section.

RFU

Reserved for Future Use

Not connected

SEN

Input

Scan enable. VDDQ CMOS input. Must be tied to the ground when not in use.

RESET#

Input

Reset Pin. VDDQ CMOS input. RESET# Low asynchronously initiates a full chip reset. With

RESET# Low all ODTs are disabled.

Table 54. Ball-out Description

SYMBOL

TYPE

DESCRIPTION

H5GQ1H24AFR-R0C 数据表(PDF) 159 Page - Hynix Semiconductor