PIC12F675T-ESLASHP datasheet(21/136 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS41190G-page 21

PIC12F629/675

3.0

GPIO PORT

There are as many as six general purpose I/O pins

available. Depending on which peripherals are

enabled, some or all of the pins may not be available as

general purpose I/O. In general, when a peripheral is

enabled, the associated pin may not be used as a

general purpose I/O pin.

3.1

GPIO and the TRISIO Registers

GPIO is an 6-bit wide, bidirectional port. The

corresponding data direction register is TRISIO.

Setting a TRISIO bit (= 1) will make the corresponding

GPIO pin an input (i.e., put the corresponding output

driver in a High-Impedance mode). Clearing a TRISIO

bit (= 0) will make the corresponding GPIO pin an

output (i.e., put the contents of the output latch on the

selected pin). The exception is GP3, which is input-only

and its TRISIO bit will always read as ‘1’. Example 3-1

shows how to initialize GPIO.

Reading the GPIO register reads the status of the pins,

whereas writing to it will write to the PORT latch. All

write operations are read-modify-write operations.

Therefore, a write to a port implies that the port pins are

read, this value is modified, and then written to the

PORT data latch. GP3 reads ‘0’ when MCLREN = 1.

The TRISIO register controls the direction of the

GP pins, even when they are being used as analog

inputs. The user must ensure the bits in the TRISIO

inputs. I/O pins configured as analog inputs always

read ‘0’.

EXAMPLE 3-1:

INITIALIZING GPIO

3.2

Additional Pin Functions

Every GPIO pin on the PIC12F629/675 has an

interrupt-on-change option and every GPIO pin, except

GP3, has a weak pull-up option. The next two sections

describe these functions.

3.2.1

WEAK PULL-UP

Each of the GPIO pins, except GP3, has an individually

configurable weak internal pull-up. Control bits WPUx

enable or disable each pull-up. Refer to Register 3-3.

Each weak pull-up is automatically turned off when the

port pin is configured as an output. The pull-ups are

disabled on a Power-on Reset by the GPPU bit

(OPTION<7>).

GPIO: GPIO REGISTER (ADDRESS: 05h)

Note:

Additional information on I/O ports may be

found in the PIC® Mid-Range Reference

Manual, (DS33023).

Note:

The ANSEL (9Fh) and CMCON (19h)

registers (9Fh) must be initialized to

configure an analog channel as a digital

input. Pins configured as analog inputs will

read ‘0’. The ANSEL register is defined for

the PIC12F675.

BCF

STATUS,RP0

;Bank 0

CLRF

GPIO

;Init GPIO

MOVLW

07h

;Set GP<2:0> to

MOVWF

CMCON

;digital IO

BSF

STATUS,RP0

;Bank 1

CLRF

ANSEL

;Digital I/O

MOVLW

0Ch

;Set GP<3:2> as inputs

MOVWF

TRISIO

;and set GP<5:4,1:0>

;as outputs

U-0

R/W-x

—

GPIO5

GPIO4

GPIO3

GPIO2

GPIO1

GPIO0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

Unimplemented: Read as ‘0’

bit 5-0

GPIO<5:0>: General Purpose I/O pin

1 = Port pin is >VIH

0 = Port pin is <VIL

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