PIC12F675T-ESLASHP datasheet(23/136 Pages) MICROCHIP

23 / 136 page

 2010 Microchip Technology Inc.

DS41190G-page 23

PIC12F629/675

3.2.2

INTERRUPT-ON-CHANGE

Each of the GPIO pins is individually configurable as an

interrupt-on-change pin. Control bits IOC enable or

disable the interrupt function for each pin. Refer to

Power-on Reset.

For enabled interrupt-on-change pins, the values are

compared with the old value latched on the last read of

GPIO. The ‘mismatch’ outputs of the last read are OR’d

together to set, the GP Port Change Interrupt flag bit

(GPIF) in the INTCON register.

This interrupt can wake the device from Sleep. The

user, in the Interrupt Service Routine, can clear the

interrupt in the following manner:

Any read or write of GPIO. This will end the

mismatch condition.

b) Clear the flag bit GPIF.

A mismatch condition will continue to set flag bit GPIF.

Reading GPIO will end the mismatch condition and

allow flag bit GPIF to be cleared.

IOC: INTERRUPT-ON-CHANGE GPIO REGISTER (ADDRESS: 96h)

Note:

If a change on the I/O pin should occur

when the read operation is being executed

(start of the Q2 cycle), then the GPIF inter-

rupt flag may not get set.

U-0

R/W-0

—

IOC5

IOC4

IOC3

IOC2

IOC1

IOC0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

Unimplemented: Read as ‘0’

bit 5-0

IOC<5:0>: Interrupt-on-Change GPIO Control bits

1 = Interrupt-on-change enabled

0 = Interrupt-on-change disabled

Note 1:

Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized.

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