PIC12F675T-ESLASHP datasheet(15/136 Pages) MICROCHIP

15 / 136 page

 2010 Microchip Technology Inc.

DS41190G-page 15

PIC12F629/675

2.2.2.3

INTCON Register

The INTCON register is a readable and writable

for TMR0 register overflow, GPIO port change and

external GP2/INT pin interrupts.

INTCON: INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh OR 8Bh)

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User soft-

ware should ensure the appropriate

interrupt flag bits are clear prior to enabling

an interrupt.

R/W-0

GIE

PEIE

T0IE

INTE

GPIE

T0IF

INTF

GPIF

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts

0 = Disables all interrupts

bit 6

PEIE: Peripheral Interrupt Enable bit

1 = Enables all unmasked peripheral interrupts

0 = Disables all peripheral interrupts

bit 5

T0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 interrupt

0 = Disables the TMR0 interrupt

bit 4

INTE: GP2/INT External Interrupt Enable bit

1 = Enables the GP2/INT external interrupt

0 = Disables the GP2/INT external interrupt

bit 3

GPIE: Port Change Interrupt Enable bit(1)

1 = Enables the GPIO port change interrupt

0 = Disables the GPIO port change interrupt

bit 2

T0IF: TMR0 Overflow Interrupt Flag bit(2)

1 = TMR0 register has overflowed (must be cleared in software)

0 = TMR0 register did not overflow

bit 1

INTF: GP2/INT External Interrupt Flag bit

1 = The GP2/INT external interrupt occurred (must be cleared in software)

0 = The GP2/INT external interrupt did not occur

bit 0

GPIF: Port Change Interrupt Flag bit

1 = When at least one of the GP5:GP0 pins changed state (must be cleared in software)

0 = None of the GP5:GP0 pins have changed state

Note 1:

IOC register must also be enabled to enable an interrupt-on-change.

T0IF bit is set when TIMER0 rolls over. TIMER0 is unchanged on Reset and should be initialized before

clearing T0IF bit.

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