PIC12F675T-ESLASHP datasheet(51/136 Pages) MICROCHIP

51 / 136 page

 2010 Microchip Technology Inc.

DS41190G-page 51

PIC12F629/675

8.3

Reading the EEPROM Data

Memory

To read a data memory location, the user must write

the address to the EEADR register and then set

control bit RD (EECON1<0>), as shown in

Example 8-1. The data is available, in the very next

cycle, in the EEDATA register. Therefore, it can be

read in the next instruction. EEDATA holds this value

until another read, or until it is written to by the user

(during a write operation).

EXAMPLE 8-1:

DATA EEPROM READ

8.4

Writing to the EEPROM Data

Memory

To write an EEPROM data location, the user must first

write the address to the EEADR register and the data

to the EEDATA register. Then the user must follow a

specific sequence to initiate the write for each byte, as

shown in Example 8-2.

EXAMPLE 8-2:

DATA EEPROM WRITE

The write will not initiate if the above sequence is not

exactly followed (write 55h to EECON2, write AAh to

EECON2, then set WR bit) for each byte. We strongly

recommend that interrupts be disabled during this

code segment. A cycle count is executed during the

required sequence. Any number that is not equal to the

required cycles to execute the required sequence will

prevent the data from being written into the EEPROM.

Additionally, the WREN bit in EECON1 must be set to

enable write. This mechanism prevents accidental

writes to data EEPROM due to errant (unexpected)

code execution (i.e., lost programs). The user should

keep the WREN bit clear at all times, except when

updating EEPROM. The WREN bit is not cleared

by hardware.

After a write sequence has been initiated, clearing the

WREN bit will not affect this write cycle. The WR bit will

be inhibited from being set unless the WREN bit is set.

At the completion of the write cycle, the WR bit is

cleared in hardware and the EE Write Complete

Interrupt Flag bit (EEIF) is set. The user can either

enable this interrupt or poll this bit. The EEIF bit

(PIR<7>) register must be cleared by software.

8.5

Write Verify

Depending on the application, good programming

practice may dictate that the value written to the data

EEPROM should be verified (see Example 8-3) to the

desired value to be written.

EXAMPLE 8-3:

WRITE VERIFY

8.5.1

USING THE DATA EEPROM

The data EEPROM is a high-endurance, byte

addressable array that has been optimized for the

storage of frequently changing information (e.g.,

program variables or other data that are updated

often). Frequently changing values will typically be

updated more often than specifications D120 or

D120A. If this is not the case, an array refresh must be

performed. For this reason, variables that change

infrequently (such as constants, IDs, calibration, etc.)

should be stored in Flash program memory.

8.6

Protection Against Spurious Write

There are conditions when the device may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been built in. On power-up, WREN is cleared. Also, the

Power-up

Timer

(72

duration)

prevents

EEPROM write.

The write initiate sequence and the WREN bit together

help prevent an accidental write during:

•brown-out

• power glitch

• software malfunction

BSF

STATUS,RP0

;Bank 1

MOVLW CONFIG_ADDR

;

MOVWF EEADR

;Address to read

BSF

EECON1,RD

;EE Read

MOVF

EEDATA,W

;Move data to W

BSF

STATUS,RP0

;Bank 1

BSF

EECON1,WREN

;Enable write

BCF

INTCON,GIE

;Disable INTs

MOVLW 55h

;Unlock write

MOVWF EECON2

;

MOVLW AAh

;

MOVWF EECON2

;

BSF

EECON1,WR

;Start the write

BSF

INTCON,GIE

;Enable INTS

BCF

STATUS,RP0

;Bank 0

;Any code

BSF

STATUS,RP0

;Bank 1 READ

MOVF

EEDATA,W

;EEDATA not changed

;from previous write

BSF

EECON1,RD

;YES, Read the

;value written

XORWF EEDATA,W

BTFSS STATUS,Z

;Is data the same

GOTO

WRITE_ERR

;No, handle error

;Yes, continue

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