PIC12F675T-ESLASHP datasheet(17/136 Pages) MICROCHIP

17 / 136 page

 2010 Microchip Technology Inc.

DS41190G-page 17

PIC12F629/675

2.2.2.5

PIR1 Register

The PIR1 register contains the interrupt flag bits, as

shown in Register 2-5.

PIR1: PERIPHERAL INTERRUPT REGISTER 1 (ADDRESS: 0Ch)

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User

software should ensure the appropriate

interrupt flag bits are clear prior to enabling

an interrupt.

R/W-0

U-0

R/W-0

U-0

R/W-0

EEIF

ADIF

—

—CMIF

—

—TMR1IF

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

EEIF: EEPROM Write Operation Interrupt Flag bit

1 = The write operation completed (must be cleared in software)

0 = The write operation has not completed or has not been started

bit 6

ADIF: A/D Converter Interrupt Flag bit (PIC12F675 only)

1 = The A/D conversion is complete (must be cleared in software)

0 = The A/D conversion is not complete

bit 5-4

Unimplemented: Read as ‘0’

bit 3

CMIF: Comparator Interrupt Flag bit

1 = Comparator input has changed (must be cleared in software)

0 = Comparator input has not changed

bit 2-1

Unimplemented: Read as ‘0’

bit 0

TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overflowed (must be cleared in software)

0 = TMR1 register did not overflow

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