PIC12F675T-ESLASHP datasheet(57/136 Pages) MICROCHIP

57 / 136 page

 2010 Microchip Technology Inc.

DS41190G-page 57

PIC12F629/675

9.3

Reset

The PIC12F629/675 differentiates between various

kinds of Reset:

Power-on Reset (POR)

WDT Reset during normal operation

WDT Reset during Sleep

MCLR Reset during normal operation

MCLR Reset during Sleep

Brown-out Detect (BOD)

Some registers are not affected in any Reset condition;

their status is unknown on POR and unchanged in any

other Reset. Most other registers are reset to a “Reset

state” on:

• Power-on Reset

•MCLR Reset

•WDT Reset

• WDT Reset during Sleep

• Brown-out Detect (BOD) Reset

They are not affected by a WDT wake-up, since this is

viewed as the resumption of normal operation. TO and

PD bits are set or cleared differently in different Reset

situations as indicated in Table 9-4. These bits are

used in software to determine the nature of the Reset.

See Table 9-7 for a full description of Reset states of all

registers.

A simplified block diagram of the on-chip Reset Circuit

is shown in Figure 9-4.

The MCLR Reset path has a noise filter to detect and

ignore small pulses. See Table 12-4 in Electrical

Specifications Section for pulse-width specification.

FIGURE 9-4:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

Reset

MCLR/

VDD

OSC1/

WDT

Module

VDD Rise

Detect

OST/PWRT

On-chip(1)

RC OSC

WDT

Time-out

Power-on Reset

OST

PWRT

Chip_Reset

10-bit Ripple Counter

Reset

Enable OST

Enable PWRT

SLEEP

See Table 9-3 for time-out situations.

Note

This is a separate oscillator from the INTOSC/EC oscillator.

Brown-out

Detect

BODEN

CLKIN

VPP pin

10-bit Ripple Counter

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