PIC12F675T-ESLASHP datasheet(66/136 Pages) MICROCHIP

66 / 136 page

PIC12F629/675

DS41190G-page 66

 2010 Microchip Technology Inc.

TABLE 9-8:

SUMMARY OF INTERRUPT REGISTERS

9.5

Context Saving During Interrupts

During an interrupt, only the return PC value is saved

on the stack. Typically, users may wish to save key

registers during an interrupt (e.g., W register and

STATUS register). This must be implemented in

software.

Example 9-2 stores and restores the STATUS and W

registers. The user register, W_TEMP, must be defined

in both banks and must be defined at the same offset

from the bank base address (i.e., W_TEMP is defined

at 0x20 in Bank 0 and it must also be defined at 0xA0

in Bank 1). The user register, STATUS_TEMP, must be

defined in Bank 0. The Example 9-2:

• Stores the W register

• Stores the STATUS register in Bank 0

• Executes the ISR code

• Restores the STATUS (and bank select bit

• Restores the W register

EXAMPLE 9-2:

SAVING THE STATUS AND

W REGISTERS IN RAM

9.6

Watchdog Timer (WDT)

The Watchdog Timer is a free running, on-chip RC

oscillator, which requires no external components. This

RC oscillator is separate from the external RC oscillator

of the CLKIN pin and INTOSC. That means that the

WDT will run, even if the clock on the OSC1 and OSC2

pins of the device has been stopped (for example, by

execution of a SLEEP instruction). During normal

operation, a WDT Time-out generates a device Reset.

If the device is in Sleep mode, a WDT Time-out causes

the device to wake-up and continue with normal

operation. The WDT can be permanently disabled by

programming the Configuration bit WDTE as clear

(Section 9.1 “Configuration Bits”).

9.6.1

WDT PERIOD

The WDT has a nominal time-out period of 18 ms, (with

no prescaler). The time-out periods vary with

temperature, VDD and process variations from part to

part (see DC specs). If longer time-out periods are

desired, a prescaler with a division ratio of up to 1:128

can be assigned to the WDT under software control by

writing to the OPTION register. Thus, time-out periods

up to 2.3 seconds can be realized.

The CLRWDT and SLEEP instructions clear the WDT

and the prescaler, if assigned to the WDT, and prevent

it from timing out and generating a device Reset.

The TO bit in the STATUS register will be cleared upon

a Watchdog Timer Time-out.

9.6.2

WDT PROGRAMMING

CONSIDERATIONS

It should also be taken in account that under worst-

case conditions (i.e., VDD = Min., Temperature = Max.,

Max. WDT prescaler) it may take several seconds

before a WDT Time-out occurs.

Address

Name

Bit 7Bit 6Bit 5

Bit 4Bit 3Bit 2

Bit 1Bit 0

Value on

POR, BOD

Value on all

other

Resets

0Bh, 8Bh INTCON

GIE

PEIE

T0IE

INTE

GPIE

T0IF

INTF

GPIF

0000 0000 0000 000u

0Ch

PIR1

EEIF

ADIF

—

—CMIF

—

—TMR1IF 00-- 0--0 00-- 0--0

8Ch

PIE1

EEIE

ADIE

—

—CMIE

—

—TMR1IE 00-- 0--0 00-- 0--0

Legend:

x = unknown, u = unchanged, - = unimplemented read as ‘0’, q = value depends upon condition.

Shaded cells are not used by the interrupt module.

MOVWF

W_TEMP

;copy W to temp register,

could be in either bank

SWAPF

STATUS,W

;swap status to be saved into W

BCF

STATUS,RP0

;change to bank 0 regardless of

current bank

MOVWF

STATUS_TEMP

;save status to bank 0 register

:(ISR)

SWAPF

STATUS_TEMP,W;swap STATUS_TEMP register into

W, sets bank to original state

MOVWF

STATUS

;move W into STATUS register

SWAPF

W_TEMP,F

;swap W_TEMP

SWAPF

W_TEMP,W

;swap W_TEMP into W

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