PIC12F675T-ESLASHP datasheet(41/136 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS41190G-page 41

PIC12F629/675

6.5

Comparator Reference

The comparator module also allows the selection of an

internally generated voltage reference for one of the

comparator inputs. The internal reference signal is

used for four of the eight Comparator modes. The

VRCON register, Register 6-2, controls the voltage

reference module shown in Figure 6-5.

6.5.1

CONFIGURING THE VOLTAGE

REFERENCE

The voltage reference can output 32 distinct voltage

levels, 16 in a high range and 16 in a low range.

The following equations determine the output voltages:

6.5.2

VOLTAGE REFERENCE

ACCURACY/ERROR

The full range of VSS to VDD cannot be realized due to

the construction of the module. The transistors on the

top and bottom of the resistor ladder network

(Figure 6-5) keep CVREF from approaching VSS or

VDD. The Voltage Reference is VDD derived and there-

fore, the CVREF output changes with fluctuations in

VDD. The tested absolute accuracy of the Comparator

Voltage Reference can be found in Section 12.0

“Electrical Specifications”.

FIGURE 6-5:

COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

6.6

Comparator Response Time

Response time is the minimum time, after selecting a

new reference voltage or input source, before the

comparator output is ensured to have a valid level. If

the internal reference is changed, the maximum delay

of the internal voltage reference must be considered

when using the comparator outputs. Otherwise, the

maximum delay of the comparators should be used

(Table 12-7).

6.7

Operation During Sleep

Both the comparator and voltage reference, if enabled

before entering Sleep mode, remain active during

Sleep. This results in higher Sleep currents than shown

in the power-down specifications. The additional cur-

rent consumed by the comparator and the voltage ref-

erence is shown separately in the specifications. To

minimize power consumption while in Sleep mode, turn

off the comparator, CM2:CM0 = 111, and voltage refer-

ence, VRCON<7> = 0.

While the comparator is enabled during Sleep, an inter-

rupt will wake-up the device. If the device wakes up

from Sleep, the contents of the CMCON and VRCON

registers are not affected.

6.8

Effects of a Reset

A device Reset forces the CMCON and VRCON

registers to their Reset states. This forces the

comparator module to be in the Comparator Reset

mode, CM2:CM0 = 000 and the voltage reference to its

off state. Thus, all potential inputs are analog inputs

with the comparator and voltage reference disabled to

consume the smallest current possible.

VRR = 1 (low range): CVREF = (VR3:VR0 / 24) x VDD

VRR = 0 (high range): CVREF = (VDD / 4) + (VR3:VR0 x

VDD / 32)

VRR

VR3:VR0

16-1 Analog

CVREF to

16 Stages

Comparator

Input

VREN

VDD

MUX

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