PIC12F675T-ESLASHP datasheet(19/136 Pages) MICROCHIP

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DS41190G-page 19

PIC12F629/675

2.3

PCL and PCLATH

The Program Counter (PC) is 13-bits wide. The low byte

comes from the PCL register, which is a readable and

writable register. The high byte (PC<12:8>) is not

directly readable or writable and comes from PCLATH.

On any Reset, the PC is cleared. Figure 2-3 shows the

two situations for the loading of the PC. The upper

example in Figure 2-3 shows how the PC is loaded on

a write to PCL (PCLATH<4:0>

 PCH). The lower

example in Figure 2-3 shows how the PC is loaded

during a CALL or GOTO instruction (PCLATH<4:3>



PCH).

FIGURE 2-3:

LOADING OF PC IN

DIFFERENT SITUATIONS

2.3.1

COMPUTED GOTO

A computed GOTO is accomplished by adding an offset

to the PC (ADDWF PCL). When performing a table read

using a computed GOTO method, care should be

exercised if the table location crosses a PCL memory

boundary (each 256-byte block). Refer to the

Application Note, “Implementing a Table Read”

(AN556).

2.3.2

STACK

The PIC12F629/675 family has an 8-level deep x 13-bit

wide hardware stack (see Figure 2-1). The stack space

is not part of either program or data space and the

Stack Pointer is not readable or writable. The PC is

PUSHed onto the stack when a CALL instruction is

executed, or an interrupt causes a branch. The stack is

POPed in the event of a RETURN, RETLW or a RETFIE

instruction execution. PCLATH is not affected by a

PUSH or POP operation.

The stack operates as a circular buffer. This means that

after the stack has been PUSHed eight times, the ninth

push overwrites the value that was stored from the first

push. The tenth push overwrites the second push (and

so on).

8 7

PCLATH<4:0>

PCLATH

Instruction with

ALU result

GOTO, CALL

Opcode <10:0>

12 11 10

PCLATH<4:3>

PCH

PCL

PCLATH

PCH

PCL

PCL as

Destination

Note 1: There are no Status bits to indicate Stack

Overflow or Stack Underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL,

RETURN,

RETLW

and RETFIE

instructions, or the vectoring to an

interrupt address.

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