PIC12F675T-ESLASHP datasheet(9/136 Pages) MICROCHIP

9 / 136 page

 2010 Microchip Technology Inc.

DS41190G-page 9

PIC12F629/675

2.0

MEMORY ORGANIZATION

2.1

Program Memory Organization

The PIC12F629/675 devices have a 13-bit program

counter capable of addressing an 8K x 14 program

memory space. Only the first 1K x 14 (0000h-03FFh)

for the PIC12F629/675 devices is physically imple-

mented. Accessing a location above these boundaries

will cause a wrap-around within the first 1K x 14 space.

The Reset vector is at 0000h and the interrupt vector is

at 0004h (see Figure 2-1).

FIGURE 2-1:

PROGRAM MEMORY MAP

AND STACK FOR THE

DSTEMP/675

2.2

Data Memory Organization

The data memory (see Figure 2-2) is partitioned into

two banks, which contain the General Purpose

Registers and the Special Function Registers. The

Special Function Registers are located in the first 32

locations of each bank. Register locations 20h-5Fh are

General Purpose Registers, implemented as static

RAM and are mapped across both banks. All other

RAM is unimplemented and returns ‘0’ when read. RP0

(STATUS<5>) is the bank select bit.

•RP0 = 0 Bank 0 is selected

•RP0 = 1 Bank 1 is selected

2.2.1

GENERAL PURPOSE REGISTER

FILE

The register file is organized as 64 x 8 in the

PIC12F629/675 devices. Each register is accessed,

either directly or indirectly, through the File Select

INDF and FSR Registers”).

PC<12:0>

000h

0004

0005

03FFh

0400h

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN

RETFIE, RETLW

Stack Level 2

Note:

The IRP and RP1 bits STATUS<7:6> are

reserved and should always be maintained

as ‘0’s.

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