EM357-RTR datasheet(103/240 Pages) ETC2

103 / 240 page

EM351 / EM357

8-32

120-035X-000D

Preliminary

SC1_UARTFRAC

UART Baud Rate Fractional Period Register

Address: 0x4000C86C Reset: 0x0

SC_UARTFRAC

Bitname

Bitfield

Access

Description

SC_UARTFRAC

[0]

The fractional part of the baud rate period (F) in the equation:

rate = 24MHz / ( (2 * N) + F )

8.7

DMA Channels

The EM35x serial DMA channels enable efficient, high-speed operation of the SPI and UART controllers by

reducing the load on the CPU as well as decreasing the frequency of interrupts that it must service. The

transmit and receive DMA channels can transfer data between the transmit and receive FIFOs and the DMA

buffers in main memory as quickly as it can be transmitted or received. Once software defines, configures,

and activates the DMA, it only needs to handle an interrupt when a transmit buffer has been emptied or a

receive buffer has been filled. The DMA channels each support two memory buffers, labeled A and B, and can

alternate (“ping-pong”) between them automatically to allow continuous communication without critical

interrupt timing.

Note:

DMA memory buffer terminology

load - make a buffer available for the DMA channel to use

pending – a buffer loaded but not yet active

active - the buffer that will be used for the next DMA transfer

unload – DMA channel action when it has finished with a buffer

idle – a buffer that has not been loaded, or has been unloaded

To use a DMA channel, software should follow these steps:

Reset the DMA channel by setting the SC_TXDMARST (or SC_RXDMARST) bit in the SCx_DMACTRL register.

Set up the DMA buffers. The two DMA buffers, A and B, are defined by writing the start address to

SCx_TXBEGA/B (or SCx_RXBEGA/B) and the (inclusive) end address to SCx_TXENDA/B (or SCx_RXENDA/B).

Note that DMA buffers must be in RAM.

Configure and initialize SCx for the desired operating mode.

Enable second-level interrupts triggered when DMA buffers unload by setting the INT_SCTXULDA/B (or

INT_SCRXULDA/B) bits in the INT_SCxFLAG register.

Enable top-level NVIC interrupts by setting the INT_SCx bit in the INT_CFGSET register.

Start the DMA by loading the DMA buffers by setting the SC_TXLODA/B (or SC_RXLODA/B) bits in the

SCx_DMACTRL register.

A DMA buffer’s end address, SCx_TXENDA/B (or SCx_RXENDA/B), can be written while the buffer is loaded or

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