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数据搜索系统，热门电子元器件搜索 |
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EM357-RTR 数据表(PDF) 106 Page - List of Unclassifed Manufacturers |
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EM357-RTR 数据表(HTML) 106 Page - List of Unclassifed Manufacturers |
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106 / 240 page  EM351 / EM357 SCx_DMASTAT SC1_DMASTAT Serial DMA Status Register Address: 0x4000C82C Reset: 0x0 SC2_DMASTAT Serial DMA Status Register Address: 0x4000C02C Reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 SC_RXSSEL SC_RXFRMB SC_RXFRMA 7 6 5 4 3 2 1 0 SC_RXPARB SC_RXPARA SC_RXOVFB SC_RXOVFA SC_TXACTB SC_TXACTA SC_RXACTB SC_RXACTA Bitname Bitfield Access Description SC_RXSSEL [12:10] R Status of the receive count saved in SCx_RXCNTSAVED (SPI slave mode) when nSSEL deasserts. Cleared when a receive buffer is loaded and when the receive DMA is reset. 0: No count was saved because nSSEL did not deassert. 2: Buffer A's count was saved, nSSEL deasserted once. 3: Buffer B's count was saved, nSSEL deasserted once. 6: Buffer A's count was saved, nSSEL deasserted more than once. 7: Buffer B's count was saved, nSSEL deasserted more than once. 1, 4, 5: Reserved. SC_RXFRMB [9] R This bit is set when DMA receive buffer B reads a byte with a frame error from the receive FIFO. It is cleared the next time buffer B is loaded or when the receive DMA is reset. (SC1 in UART mode only) SC_RXFRMA [8] R This bit is set when DMA receive buffer A reads a byte with a frame error from the receive FIFO. It is cleared the next time buffer A is loaded or when the receive DMA is reset. (SC1 in UART mode only) SC_RXPARB [7] R This bit is set when DMA receive buffer B reads a byte with a parity error from the receive FIFO. It is cleared the next time buffer B is loaded or when the receive DMA is reset. (SC1 in UART mode only) SC_RXPARA [6] R This bit is set when DMA receive buffer A reads a byte with a parity error from the receive FIFO. It is cleared the next time buffer A is loaded or when the receive DMA is reset. (SC1 in UART mode only) SC_RXOVFB [5] R This bit is set when DMA receive buffer B was passed an overrun error from the receive FIFO. Neither receive buffer was capable of accepting any more bytes (unloaded), and the FIFO filled up. Buffer B was the next buffer to load, and when it drained the FIFO the overrun error was passed up to the DMA and flagged with this bit. Cleared the next time buffer B is loaded and when the receive DMA is reset. SC_RXOVFA [4] R This bit is set when DMA receive buffer A was passed an overrun error from the receive FIFO. Neither receive buffer was capable of accepting any more bytes (unloaded), and the FIFO filled up. Buffer A was the next buffer to load, and when it drained the FIFO the overrun error was passed up to the DMA and flagged with this bit. Cleared the next time buffer A is loaded and when the receive DMA is reset. SC_TXACTB [3] R This bit is set when DMA transmit buffer B is active. SC_TXACTA [2] R This bit is set when DMA transmit buffer A is active. SC_RXACTB [1] R This bit is set when DMA receive buffer B is active. SC_RXACTA [0] R This bit is set when DMA receive buffer A is active. 8-35 120-035X-000D Preliminary |
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