EM357-RTR datasheet(153/240 Pages) ETC2

153 / 240 page

EM351 / EM357

TIMx_CR2

TIM1_CR2

Timer 1 Control Register 2

Address: 0x4000E004 Reset: 0x0

TIM2_CR2

Timer 2 Control Register 2

Address: 0x4000F004 Reset: 0x0

TIM_TI1S

TIM_MMS

Bitname

Bitfield

Access

Description

TIM_TI1S

[7]

TI1 Selection.

0: TI1M (input of the digital filter) is connected to TI1 input.

1: TI1M is connected to the TI_HALL inputs (XOR combination).

TIM_MMS

[6:4]

Master Mode Selection.

This selects the information to be sent in master mode to a slave timer for

synchronization using the trigger output (TRGO).

000: Reset - the TIM_UG bit in the TMRx_EGR register is trigger output.

If the reset is generated by the trigger input (slave mode controller configured in reset

mode), then the signal on TRGO is delayed compared to the actual reset.

001: Enable - counter enable signal CNT_EN is trigger output.

This mode is used to start both timers at the same time or to control a window in which a

slave timer is enabled. The counter enable signal is generated by either the TIM_CEN

control bit or the trigger input when configured in gated mode. When the counter enable

signal is controlled by the trigger input there is a delay on TRGO except if the

master/slave mode is selected (see the TIM_MSM bit description in TMRx_SMCR register).

010: Update - UEV is trigger output.

This mode allows a master timer to be a prescaler for a slave timer.

011: Compare Pulse.

The trigger output sends a positive pulse when the TIM_CC1IF flag is to be set (even if it

was already high) as soon as a capture or a compare match occurs.

100: Compare - OC1REF signal is trigger output.

101: Compare - OC2REF signal is trigger output.

110: Compare - OC3REF signal is trigger output.

111: Compare - OC4REF signal is trigger output.

9-33

120-035X-000D

Preliminary

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