EM357-RTR datasheet(157/240 Pages) ETC2

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EM351 / EM357

TIM1_CCMR1

Timer 1 Capture/Compare Mode Register 1

Address: 0x4000E018 Reset: 0x0

TIM2_CCMR1

Timer 2 Capture/Compare Mode Register 1

Address: 0x4000F018 Reset: 0x0

TIM_OC2M

TIM_OC2BE

TIM_OC2FE

TIM_IC2F

TIM_IC2PSC

TIM_CC2S

TIM_OC1M

TIM_OC1BE

TIM_OC1FE

TIM_IC1F

TIM_IC1PSC

TIM_CC1S

Timer channels can be programmed as inputs (capture mode) or outputs (compare mode). The direction of channel y is defined by TIM_CCyS in this

The other bits in this register have different functions in input and in output modes. The TIM_OC* fields only apply to a channel configured as an

output (TIM_CCyS = 0), and the TIM_IC* fields only apply to a channel configured as an input (TIM_CCyS > 0).

Bitname

Bitfield

Access

Description

TIM_OC2M

[14:12]

Output Compare 2 Mode. (Applies only if TIM_CC2S = 0.)

Define the behavior of the output reference signal OC2REF from which OC2 derives.

OC2REF is active high whereas OC2''s active level depends on the TIM_CC2P bit.

000: Frozen - The comparison between the output compare register TIMx_CCR2 and the

counter TIMx_CNT has no effect on the outputs.

001: Set OC2REF to active on match. The OC2REF signal is forced high when the counter

TIMx_CNT matches the capture/compare register 2 (TIMx_CCR2)

010: Set OC2REF to inactive on match. OC2REF signal is forced low when the counter

TIMx_CNT matches the capture/compare register 2 (TIMx_CCR2).

011: Toggle - OC2REF toggles when TIMx_CNT = TIMx_CCR2.

100: Force OC2REF inactive.

101: Force OC2REF active.

110: PWM mode 1 - In up-counting, OC2REF is active as long as TIMx_CNT < TIMx_CCR2,

otherwise OC2REF is inactive. In down-counting, OC2REF is inactive if

TIMx_CNT > TIMx_CCR2, otherwise OC2REF is active.

111: PWM mode 2 - In up-counting, OC2REF is inactive if TIMx_CNT < TIMx_CCR2,

otherwise OC2REF is active. In down-counting, OC2REF is active if TIMx_CNT > TIMx_CCR2,

otherwise it is inactive.

Note: In PWM mode 1 or 2, the OC2REF level changes only when the result of the

comparison changes or when the output compare mode switches from “frozen” mode to

“PWM” mode.

TIM_OC2BE

[11]

Output Compare 2 Buffer Enable. (Applies only if TIM_CC2S = 0.)

0: Buffer register for TIMx_CCR2 is disabled. TIMx_CCR2 can be written at anytime, the

new value is used by the shadow register immediately.

1: Buffer register for TIMx_CCR2 is enabled. Read/write operations access the buffer

Note: The PWM mode can be used without enabling the buffer register only in one pulse

mode (TIM_OPM bit set in the TIMx_CR2 register), otherwise the behavior is undefined.

9-37

120-035X-000D

Preliminary

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