EM357-RTR datasheet(160/240 Pages) ETC2

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EM351 / EM357

TIMx_CCMR2

TIM1_CCMR2

Timer 1 Capture/Compare Mode Register 2

Address: 0x4000E01C Reset: 0x0

TIM2_CCMR2

Timer 2 Capture/Compare Mode Register 2

Address: 0x4000F01C Reset: 0x0

TIM_OC4M

TIM_OC4BE

TIM_OC4FE

TIM_IC4F

TIM_IC4PSC

TIM_CC4S

TIM_OC3M

TIM_OC3BE

TIM_OC3FE

TIM_IC3F

TIM_IC3PSC

TIM_CC3S

Timer channels can be programmed as inputs (capture mode) or outputs (compare mode). The direction of channel y is defined by TIM_CCyS in this

The other bits in this register have different functions in input and in output modes. The TIM_OC* fields only apply to a channel configured as an

output (TIM_CCyS = 0), and the TIM_IC* fields only apply to a channel configured as an input (TIM_CCyS > 0).

Bitname

Bitfield

Access

Description

TIM_OC4M

[14:12]

Output Compare 4 Mode. (Applies only if TIM_CC4S = 0.)

Define the behavior of the output reference signal OC4REF from which OC4 derives.

OC4REF is active high whereas OC4’s active level depends on the TIM_CC4P bit.

000: Frozen - The comparison between the output compare register TIMx_CCR4 and the

counter TIMx_CNT has no effect on the outputs.

001: Set OC4REF to active on match. The OC4REF signal is forced high when the counter

TIMx_CNT matches the capture/compare register 4 (TIMx_CCR4)

010: Set OC4REF to inactive on match. OC4REF signal is forced low when the counter

TIMx_CNT matches the capture/compare register 4 (TIMx_CCR4).

011: Toggle - OC4REF toggles when TIMx_CNT = TIMx_CCR4.

100: Force OC4REF inactive.

101: Force OC4REF active.

110: PWM mode 1 - In up-counting, OC4REF is active as long as TIMx_CNT < TIMx_CCR4,

otherwise OC4REF is inactive. In down-counting, OC4REF is inactive if

TIMx_CNT > TIMx_CCR4, otherwise OC4REF is active.

111: PWM mode 2 - In up-counting, OC4REF is inactive if TIMx_CNT < TIMx_CCR4,

otherwise OC4REF is active. In down-counting, OC4REF is active if TIMx_CNT > TIMx_CCR4,

otherwise it is inactive.

Note: In PWM mode 1 or 2, the OC4REF level changes only when the result of the

comparison changes or when the output compare mode switches from “frozen” mode to

“PWM” mode.

TIM_OC4BE

[11]

Output Compare 4 Buffer Enable. (Applies only if TIM_CC4S = 0.)

0: Buffer register for TIMx_CCR4 is disabled. TIMx_CCR4 can be written at anytime, the

new value is used by the shadow register immediately.

1: Buffer register for TIMx_CCR4 is enabled. Read/write operations access the buffer

Note: The PWM mode can be used without enabling the buffer register only in one pulse

mode (TIM_OPM bit set in the TIMx_CR2 register), otherwise the behavior is undefined.

9-40

120-035X-000D

Preliminary

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