| 数据搜索系统,热门电子元器件搜索 |
|
EM357-RTR 数据表(PDF) 167 Page - List of Unclassifed Manufacturers |
|
|
|||||||||||||||||||||||||||||
EM357-RTR 数据表(HTML) 167 Page - List of Unclassifed Manufacturers |
|
167 / 240 page ![]() EM351 / EM357 TIMx_CCR1 TIM1_CCR1 Timer 1 Capture/Compare Register 1 Address: 0x4000E034 Reset: 0x0 TIM2_CCR1 Timer 2 Capture/Compare Register 1 Address: 0x4000F034 Reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 TIM_CCR 7 6 5 4 3 2 1 0 TIM_CCR Bitname Bitfield Access Description TIM_CCR [15:0] RW If the CC1 channel is configured as an output (TIM_CC1S = 0): TIM_CCR1 is the buffer value to be loaded in the actual capture/compare 1 register. It is loaded permanently if the preload feature is not selected in the TMR1_CCMR1 register (bit OC1PE). Otherwise the buffer value is copied to the shadow capture/compare 1 register when an UEV occurs. The active capture/compare register contains the value to be compared to the counter TMR1_CNT and signaled on the OC1 output. If the CC1 channel is configured as an input (TIM_CC1S is not 0): CCR1 is the counter value transferred by the last input capture 1 event (IC1). 9-47 120-035X-000D Preliminary |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |