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Datasheet

Introduction

The Intel® Celeron® M processor based on 65 nm process technology is a high-

performance, low-power mobile processor with several enhancements over previous

mobile Celeron processors.

Throughout this document, the term “Celeron M processor” refers to the Intel®

Celeron® M processor based on 65 nm process technology.

This document contains specifications for both the Intel® Celeron® M processor 450,

440, 430, 420, 410 and Intel® Celeron® M processor Ultra Low Voltage 443 and 423Δ.

Note:

ΔIntel processor numbers are not a measure of performance. Processor numbers

differentiate features within each processor family, not across different processor

families. See http://www.intel.com/products/processor_number for details.

The following list provides some of the key features on this processor:

• On-die, 1-MB second level cache with Advanced Transfer Cache Architecture

• Supports Intel Architecture with Dynamic Execution

• On-die, primary 32-kB instruction cache and 32-kB write-back data cache

• Data Prefetch Logic

• Streaming SIMD Extensions 2 (SSE2) and Streaming SIMD Extensions 3 (SSE3)

• The Celeron M processor and the Celeron M processor Ultra Low Voltage are offered

at 533-MHz FSB

• Digital Thermal Sensor

• The Celeron M is a single core processor offered in both Micro-FCPGA and Micro-

FCBGA packages

• The Celeron M processor Ultra Low Voltage is a single core processor offered only in

a Micro-FCBGA package

• Execute Disable Bit support for enhanced security

The Celeron M processor will be manufactured on Intel’s 65 nanometer process

technology with copper interconnect. The processor maintains support for MMX™

technology, Streaming SIMD instructions, and full compatibility with IA-32 software.

The Celeron M processor features on-die, 32-kB level 1 instruction and data caches and

a 1-MB level 2 cache with Advanced Transfer Cache Architecture. The processor’s Data

Prefetch Logic speculatively fetches data to the L2 cache before the L1 cache requests

occurs, resulting in reduced bus cycle penalties. The Celeron M processor includes the

Data Cache Unit Streamer which enhances the performance of the L2 prefetcher by

requesting L1 warm-ups earlier. In addition, the Writer Order Buffer depth is enhanced

to help with the write-back latency performance.

In addition to supporting the existing Streaming SIMD Extensions 2 (SSE2), there are

13 new instructions which further extend the capabilities of Intel processor technology.

These new instructions are called Streaming SIMD Extensions 3 (SSE3). 3D graphics

and other entertainment applications such as gaming will have the opportunity to take

advantage of these new instructions as platforms with the Celeron M processor based

on 65 nm process and SSE3 become available in the market place.

The Celeron M processor’s front side bus (FSB) utilizes a split-transaction, deferred

reply protocol. The FSB uses Source-Synchronous Transfer (SST) of address and data

to improve performance by transferring data four times per bus clock. The 4X data bus

can deliver data four times per bus clock and is referred as “quad-pumped” or 4X data

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