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430 数据表(PDF) 11 Page - Intel Corporation

部件名 430
功能描述  Celeron M Processor on 65 nm Process
PDF  71 Pages
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制造商  INTEL [Intel Corporation]
网页  http://www.intel.com
标志 INTEL - Intel Corporation

430 数据表(HTML) 11 Page - Intel Corporation

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Datasheet
11
Low Power Features
2
Low Power Features
2.1
Clock Control and Low Power States
The Celeron M processor supports the C1/AutoHALT, C1/MWAIT, Stop Grant, Sleep, and
Deep Sleep for power management. See Figure 1 for a visual representation of package
level low-power states for the Celeron M processor. Package low power states include
Normal, Stop Grant, Stop Grant Snoop, Sleep and Deep Sleep. Refer Figure 2 for a
visual representation of the core low-power states for the Celeron M processor.
The Celeron M processor implements two software interfaces for requesting low power
states: MWAIT instruction extensions with sub-state hints and P_LVLx reads to the
ACPI P_BLK register block mapped in the processor’s I/O address space. The P_LVLx
I/O reads are converted to equivalent MWAIT C-state requests inside the processor and
do not directly result in I/O reads on the processor FSB. The monitor address does not
need to be setup before using the P_LVLx I/O read interface. The sub-state hints used
for each P_LVLx read can be configured through the IA32_MISC_ENABLES model
specific register (MSR).
If the processor encounters a chipset break event while STPCLK# is asserted, it asserts
the PBE# output signal. Assertion of PBE# when STPCLK# is asserted indicates to
system logic that the processor should return to the Normal state.
NOTE: (1)AutoHALT or MWAIT/C1
Table 1.
Coordination of Core-Level Low Power States at the Package Level for the
Celeron M Processor
Core States
Package States
C0
Normal
C1(1)
Normal
C2
Stop Grant
C3
Deep Sleep
Figure 1.
Package-Level Low Power States
Stop
Grant
Snoop
Normal
Stop
Grant
Deep
Sleep
STPCLK# asserted
Snoop
serviced
Snoop
occurs
Sleep
SLP# asserted
SLP# de-asserted
DPSLP# asserted
DPSLP# de-asserted
STPCLK# de-asserted



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