430 datasheet(13/71 Pages) INTEL

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Datasheet

Low Power Features

2.1.1.3

C1/MWAIT Powerdown State

MWAIT is a low power state entered when the processor core executes the MWAIT

instruction. Processor behavior in the MWAIT state is identical to the AutoHALT state

except that there is an additional event that can cause the processor core to return to

the C0 state: the Monitor event. See the IA-32 Intel® Architecture Software

Developer's Manual, Volume 2A/2B: Instruction Set Reference for more information.

2.1.1.4

Core C2 State

The core of the Celeron M processor can enter the C2 state by initiating a P_LVL2 I/O

read to the P_BLK or an MWAIT(C2) instruction, but the processor will not issue a Stop

Grant Acknowledge special bus cycle unless the STPCLK# pin is also asserted.

While in C2 state, the Celeron M processor will process only the bus snoops. The

processor core will enter a snoopable sub-state (not shown in Figure 2) to process the

snoop and then return to the C2 state.

2.1.1.5

Core C3 State

Core C3 state is a very low power state the processor core can enter while maintaining

context. The core of the Celeron M processor can enter the C3 state by initiating a

P_LVL3 I/O read to the P_BLK or an MWAIT(C3) instruction. Before entering the C3

state the processor core flushes the contents of its L1 caches into the processor’s L2

cache. Except for the caches, the processor core maintains all its architectural state in

the C3 state. The Monitor remains armed if it is configured. All of the clocks in the

processor core are stopped in the C3 state.

Because the core’s caches are flushed the processor keeps the core in the C3 state

when the processor detects a snoop on the FSB. The processor core will transition to

the C0 state upon the occurrence of a Monitor event, SMI#, INIT#, LINT[1:0] (NMI,

INTR), or FSB interrupt message. RESET# will cause the processor core to immediately

initialize itself.

2.1.2

Package Low Power States

The package level low power states are applicable for the Celeron M processor. All

package level low power states are described as follows:

2.1.2.1

Normal State

This is the normal operating state for the processor. The Celeron M processor enters the

Normal state when the core is in the C0, C1/AutoHALT, or C1/MWAIT state.

2.1.2.2

Stop-Grant State

When the STPCLK# pin is asserted the core of the Celeron M processor enters the Stop-

Grant state within 20 bus clocks after the response phase of the processor-issued Stop

Grant Acknowledge special bus cycle. When the STPCLK# pin is deasserted the core

returns to the previous core low-power state.

Since the AGTL+ signal pins receive power from the FSB, these pins should not be

driven (allowing the level to return to VCCP) for minimum power drawn by the

termination resistors in this state. In addition, all other input pins on the FSB should be

driven to the inactive state.

RESET# will cause the processor to immediately initialize itself, but the processor will

stay in Stop-Grant state. When RESET# is asserted by the system the STPCLK#, SLP#,

DPSLP#, and DPRSTP# pins must be deasserted more than 480 µs prior to RESET#

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