430 datasheet(25/71 Pages) INTEL

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Datasheet

Electrical Specifications

3.9

CMOS Signals

CMOS input signals are shown in Table 4. Legacy output FERR#, IERR# and other non-

AGTL+ signals (THERMTRIP# and PROCHOT#) utilize Open Drain output buffers. These

signals do not have setup or hold time specifications in relation to BCLK[1:0]. However,

all of the CMOS signals are required to be asserted for at least three BCLKs in order for

the processor to recognize them. See Section 3.11 for the DC specifications for the

CMOS signal groups.

3.10

Maximum Ratings

Table 5 specifies absolute maximum and minimum ratings. Only within specified

operation limits, can functionality and long-term reliability be expected.

At condition outside functional operation condition limits, but within absolute maximum

and minimum ratings, neither functionality nor long term reliability can be expected. If

a device is returned to conditions within functional operation limits after having been

subjected to conditions outside these limits, but within the absolute maximum and

minimum ratings, the device may be functional, but with its lifetime degraded on

exposure to conditions exceeding the functional operation condition limits.

At conditions exceeding absolute maximum and minimum ratings, neither functionality

nor long-term reliability can be expected. Moreover, if a device is subjected to these

conditions for any length of time then, when returned to conditions within the

functional operating condition limits, it will either not function or its reliability will be

severely degraded.

Although the processor contains protective circuitry to resist damage from electro static

discharge, precautions should always be taken to avoid high static voltages or electric

fields.

NOTES:

This rating applies to any processor pin.

Contact Intel for storage requirements in excess of one year.

3.11

Processor DC Specifications

The processor DC specifications in this section are defined at the processor

core (pads) unless noted otherwise. See Table 4 for the pin signal definitions and

signal pin assignments. Most of the signals on the FSB are in the AGTL+ signal group.

The DC specifications for these signals are listed in Table 9. DC specifications for the

CMOS group are listed in Table 10.

Table 9 through Table 11 list the DC specifications for the Celeron M processor and are

valid only while meeting specifications for junction temperature, clock frequency, and

input voltages. Active mode load line specifications apply in all states except in the

Deep Sleep state. VCC,BOOT is the default voltage driven by the voltage regulator at

Table 5.

Processor DC Absolute Maximum Ratings

Symbol

Parameter

Min

Max

Unit

Notes

TSTORAGE

Processor Storage Temperature

-40

°C

Any Processor Supply Voltage with Respect to V

-0.3

1.6

VinAGTL+

AGTL+ Buffer DC Input Voltage with Respect to V

-0.3

1.6

1, 2

VinAsynch_CMOS

CMOS Buffer DC Input Voltage with Respect to V

-0.3

1.6

1, 2

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