430 datasheet(17/71 Pages) INTEL

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Datasheet

Electrical Specifications

3.1

FSB (Front Side Bus) and GTLREF

Most Celeron M processor FSB signals use Advanced Gunning Transceiver Logic

(AGTL+) signalling technology. This signalling technology provides improved noise

margins and reduced ringing through low-voltage swings and controlled edge rates.

The termination voltage level for the Celeron M processor AGTL+ signals is VCCP =

1.05 V (nominal). Due to speed improvements to data and address bus, signal integrity

and platform design methods have become more critical than with previous processor

families. Contact your Intel representative for more information on design guidelines

for the Celeron M processor FSB.

The AGTL+ inputs require a reference voltage (GTLREF) that is used by the receivers to

determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the

system board. Termination resistors are provided on the processor silicon and are

terminated to its I/O voltage (VCCP). Intel® 945GMS and 940GML Express Chipsets will

also provide on-die termination, thus eliminating the need to terminate the bus on the

system board for most AGTL+ signals.

Refer to your Intel representative for board level termination resistor requirements.

The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for

AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog

signal simulation of the FSB, including trace lengths, is highly recommended when

designing a system.

3.2

Power and Ground Pins

For clean, on-chip power distribution, the Celeron M processor will have a large number

of VCC (power) and VSS (ground) inputs. All power pins must be connected to VCC power

planes while all VSS pins must be connected to system ground planes. Use of multiple

power and ground planes is recommended to reduce I*R drop. Please contact your

Intel representative for more details. The processor VCC pins must be supplied the

voltage determined by the VID (Voltage ID) pins.

3.3

Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is

capable of generating large average current swings between low and full power states.

This may cause voltages on power planes to sag below their minimum values if bulk

decoupling is not adequate.

Caution:

Care must be taken in the board design to ensure that the voltage provided to the

processor remains within the specifications listed in Table 6. Failure to do so can result

in timing violations or reduced lifetime of the component. For further information and

design guidelines, contact your Intel representative.

430 数据表(PDF) 17 Page - Intel Corporation

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