430 datasheet(62/71 Pages) INTEL

62 / 71 page

Package Mechanical Specifications and Pin Information

Datasheet

THERMTRIP#

Output

The processor protects itself from catastrophic overheating by use of

an internal thermal sensor. This sensor is set well above the normal

operating temperature to ensure that there are no false trips. The

processor will stop all execution when the junction temperature

exceeds approximately 125°C. This is signalled to the system by the

THERMTRIP# (Thermal Trip) pin.

For termination requirements, please contact your Intel

representative.

TMS

Input

TMS (Test Mode Select) is a JTAG specification support signal used

by debug tools.

Please contact your Intel representative for termination

requirements and implementation details.

TRDY#

Input

TRDY# (Target Ready) is asserted by the target to indicate that it is

ready to receive a write or implicit writeback data transfer. TRDY#

must connect the appropriate pins of both FSB agents.

Please contact your Intel representative for termination

requirements and implementation details.

TRST#

Input

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#

must be driven low during power on Reset.

Please contact your Intel representative for termination

requirements and implementation details.

Input

Processor core power supply.

CCA

Input

VCCA provides isolated power for the internal processor core PLL’s.

Please contact your Intel representative for complete

implementation details.

CCP

Input

Processor I/O Power Supply.

CCSENSE

Output

CCSENSE is an isolated low impedance connection to processor core

power (VCC). It can be used to sense or measure power near the

silicon with little noise. Please contact your Intel representative for

termination requirements and routing recommendations.

VID[6:0]

Output

VID[6:0] (Voltage ID) pins are used to support automatic selection

of power supply voltages (VCC). Unlike some previous generations of

processors, these are CMOS signals that are driven by the Celeron M

processor. The voltage supply for these pins must be valid before the

VR can supply Vcc to the processor. Conversely, the VR output must

be disabled until the voltage supply for the VID pins becomes valid.

The VID pins are needed to support the processor voltage

specification variations. See Table 2 for definitions of these pins. The

VR must supply the voltage that is requested by the pins, or disable

itself.

SSSENSE

Output

SSSENSE is an isolated low impedance connection to processor core

SS. It can be used to sense or measure ground near the silicon with

little noise.

Please contact your Intel representative for termination

requirements and routing recommendations.

Table 15.

Signal Description (Sheet 8 of 8)

Name

Type

Description

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