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WM8904ECS/R 数据表(PDF) 145 Page - Wolfson Microelectronics plc |
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WM8904ECS/R 数据表(HTML) 145 Page - Wolfson Microelectronics plc |
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145 / 188 page  Pre-Production WM8904 w PP, Rev 3.3, September 2012 145 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R20 (14h) Clock Rates 0 14 TOCLK_RATE _DIV16 0 TOCLK Rate Divider (/16) 0 = f / 1 1 = f / 16 Clocking and Sample Rates 13 TOCLK_RATE _X4 0 TOCLK Rate Multiplier 0 = f x 1 1 = f x 4 Clocking and Sample Rates 0 MCLK_DIV 0 Enables divide by 2 on MCLK 0 = SYSCLK = MCLK 1 = SYSCLK = MCLK / 2 Clocking and Sample Rates Register 14h Clock Rates 0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R21 (15h) Clock Rates 1 13:10 CLK_SYS_RAT E [3:0] 0011 Selects the SYSCLK / fs ratio 0000 = 64 0001 = 128 0010 = 192 0011 = 256 0100 = 384 0101 = 512 0110 = 768 0111 = 1024 1000 = 1408 1001 = 1536 Clocking and Sample Rates 2:0 SAMPLE_RAT E [2:0] 101 Selects the Sample Rate (fs) 000 = 8kHz 001 = 11.025kHz, 12kHz 010 = 16kHz 011 = 22.05kHz, 24kHz 100 = 32kHz 101 = 44.1kHz, 48kHz 110 to 111 = Reserved Clocking and Sample Rates Register 15h Clock Rates 1 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R22 (16h) Clock Rates 2 15 MCLK_INV 0 MCLK Invert 0 = MCLK not inverted 1 = MCLK inverted Clocking and Sample Rates 14 SYSCLK_SRC 0 SYSCLK Source Select 0 = MCLK 1 = FLL output Clocking and Sample Rates 12 TOCLK_RATE 0 TOCLK Rate Divider (/2) 0 = f / 2 1 = f / 1 Clocking and Sample Rates 3 OPCLK_ENA 0 GPIO Clock Output Enable 0 = disabled 1 = enabled Clocking and Sample Rates 2 CLK_SYS_EN A 0 System Clock enable 0 = Disabled 1 = Enabled Clocking and Sample Rates |
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