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WM8904ECS/R 数据表(PDF) 148 Page - Wolfson Microelectronics plc |
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WM8904ECS/R 数据表(HTML) 148 Page - Wolfson Microelectronics plc |
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148 / 188 page  WM8904 Pre-Production w PP, Rev 3.3, September 2012 148 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R26 (1Ah) Audio Interface 2 11:8 OPCLK_DIV [3:0] 0000 GPIO Output Clock Divider 0000 = SYSCLK 0001 = SYSCLK / 2 0010 = SYSCLK / 3 0011 = SYSCLK / 4 0100 = SYSCLK / 5.5 0101 = SYSCLK / 6 0110 = SYSCLK / 8 0111 = SYSCLK / 12 1000 = SYSCLK / 16 1001 to 1111 = Reserved Digital Audio Interface Control 4:0 BCLK_DIV [4:0] 0_0100 BCLK Frequency (Master Mode) 00000 = SYSCLK 00001 = SYSCLK / 1.5 00010 = SYSCLK / 2 00011 = SYSCLK / 3 00100 = SYSCLK / 4 (default) 00101 = SYSCLK / 5 00110 = SYSCLK / 5.5 00111 = SYSCLK / 6 01000 = SYSCLK / 8 01001 = SYSCLK / 10 01010 = SYSCLK / 11 01011 = SYSCLK / 12 01100 = SYSCLK / 16 01101 = SYSCLK / 20 01110 = SYSCLK / 22 01111 = SYSCLK / 24 10000 = SYSCLK / 25 10001 = SYSCLK / 30 10010 = SYSCLK / 32 10011 = SYSCLK / 44 10100 = SYSCLK / 48 Digital Audio Interface Control Register 1Ah Audio Interface 2 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R27 (1Bh) Audio Interface 3 11 LRCLK_DIR 0 Audio Interface LRC Direction 0 = LRC is input 1 = LRC is output Digital Audio Interface Control 10:0 LRCLK_RATE [10:0] 000_0100_ 0000 LRC Rate (Master Mode) LRC clock output = BCLK / LRCLK_RATE Integer (LSB = 1) Valid range: 8 to 2047 Digital Audio Interface Control Register 1Bh Audio Interface 3 |
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