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WM8904ECS/R 数据表(PDF) 147 Page - Wolfson Microelectronics plc |
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WM8904ECS/R 数据表(HTML) 147 Page - Wolfson Microelectronics plc |
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147 / 188 page  Pre-Production WM8904 w PP, Rev 3.3, September 2012 147 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R25 (19h) Audio Interface 1 13 AIFDAC_TDM 0 DAC TDM Enable 0 = Normal DACDAT operation 1 = TDM enabled on DACDAT Digital Audio Interface Control 12 AIFDAC_TDM_ CHAN 0 DACDAT TDM Channel Select 0 = DACDAT data input on slot 0 1 = DACDAT data input on slot 1 Digital Audio Interface Control 11 AIFADC_TDM 0 ADC TDM Enable 0 = Normal ADCDAT operation 1 = TDM enabled on ADCDAT Digital Audio Interface Control 10 AIFADC_TDM_ CHAN 0 ADCDAT TDM Channel Select 0 = ADCDAT outputs data on slot 0 1 = ADCDAT output data on slot 1 Digital Audio Interface Control 8 AIF_TRIS 0 Audio Interface Tristate 0 = Audio interface pins operate normally 1 = Tristate all audio interface pins Digital Audio Interface Control 7 AIF_BCLK_INV 0 BCLK Invert 0 = BCLK not inverted 1 = BCLK inverted Digital Audio Interface Control 6 BCLK_DIR 0 Audio Interface BCLK Direction 0 = BCLK is input 1 = BCLK is output Digital Audio Interface Control 4 AIF_LRCLK_IN V 0 LRC Polarity / DSP Mode A-B select. Right, left and I2S modes – LRC polarity 0 = Not Inverted 1 = Inverted DSP Mode – Mode A-B select 0 = MSB is available on 2nd BCLK rising edge after LRC rising edge (mode A) 1 = MSB is available on 1st BCLK rising edge after LRC rising edge (mode B) Digital Audio Interface Control 3:2 AIF_WL [1:0] 10 Digital Audio Interface Word Length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits Digital Audio Interface Control 1:0 AIF_FMT [1:0] 10 Digital Audio Interface Format 00 = Right Justified 01 = Left Justified 10 = I2S 11 = DSP Digital Audio Interface Control Register 19h Audio Interface 1 |
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