ADP1046AACPZ-R7 datasheet(37/88 Pages) AD

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Data Sheet

ADP1046A

Rev. 0 | Page 37 of 88

I2C INTERFACE COMMUNICATION

The ADP1046A I2C slave is a 2-wire interface that can be used

to communicate with other I2C-compliant master devices and

is compatible in a multimaster, multislave bus configuration.

The function of the I2C slave is to decode the command sent from

the master device and respond as requested. Communication is

established using a 2-wire interface with a clock line (SCL) and

data line (SDA). The I2C slave is designed to externally move

chunks of 8-bit data (bytes) while maintaining compliance with

the I2C protocol, based on the Philips I2C Bus Specification,

Version 2.1, dated January 2000. The I2C protocol incorporates

the following features:

•

Slave operation on multiple device systems

•

7-bit addressing

•

100 kB/sec and 400 kB/sec data rates

•

General call address support

•

Support for clock low extension (clock stretching)

•

Separate multiple byte receive and transmit FIFO

•

Extensive communication fault monitoring

I2C OVERVIEW

The I2C slave module is a 2-wire interface that can be used

to communicate with other I2C-compliant master devices. Its

transfer protocol is based on the I2C transfer mechanism. The

ADP1046A is always configured as a slave device in the overall

system. The ADP1046A communicates with the master device

using one data pin (SDA) and one clock pin (SCL). Because the

ADP1046A is a slave device, it cannot generate the clock signal.

However, it is capable of stretching the SCL line to place the

master device in a wait state when it is not ready to respond

to the master’s request.

Communication is initiated when the master device sends a

command to the I2C slave device. Commands can be read or

write commands, in which case data is transferred between the

devices in a byte-wide format. Commands can also be send

commands, in which case the command is executed by the slave

device upon receiving the stop bit. The stop bit is the last bit in

a complete data transfer, as defined in the I2C communication

protocol. During communication, the master and slave devices

send acknowledge (A) or no acknowledge (NA) bits as a method

of handshaking between devices. Refer to the Philips I2

C Bus

Specification, Version 2.1, dated January 2000, for a more detailed

description of the communication protocol.

I2C ADDRESS

The I2C address of the ADP1046A is set by connecting an

external resistor from the ADD pin to AGND. Table 6 lists the

recommended resistor values and the associated I2C addresses.

Seven different addresses can be used.

The recommended resistor values in Table 6 must be 1%

tolerance resistors.

Table 6. Recommended Resistor Values for I2C Addresses

I2C Address

Resistor Value (kΩ)

0x50

10 (or connect the ADD pin directly to AGND)

0x51

28.7

0x52

48.7

0x53

68.1

0x54

88.7

0x55

109

0x57

200 (or connect the ADD pin directly to VDD)

DATA TRANSFER

Format Overview

The I2C slave follows the transfer protocol of the Philips I2C Bus

Specification. Data transfers are byte-wide, lower byte first. Each

byte is transmitted serially, most significant bit (MSB) first. A

typical transfer is shown in Figure 46.

7-BIT SLAVE

ADDRESS

...

8-BIT

DATA

= MASTER-TO-SLAVE

= SLAVE-TO-MASTER

Figure 46. Basic Data Transfer

Figure 46 to Figure 53 use the following abbreviations:

•

S = start condition

•

Sr = repeated start condition

•

P = stop condition

•

R = read bit

•

W = write bit

•

A = acknowledge bit (0)

•

NA = no acknowledge bit (1)

Refer to the I2C specification for an in-depth discussion of the

transfer protocols.

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