ADP1046AACPZ-R7 datasheet(38/88 Pages) AD

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ADP1046A

Data Sheet

Rev. 0 | Page 38 of 88

Command Overview

Data transfer using the I2C slave is established using commands.

All commands start with a slave address with the R/W bit cleared

(set to 0), followed by the command code (register address). All

commands supported by the ADP1046A follow one of the protocol

types shown in Figure 47 to Figure 53.

7-BIT SLAVE

ADDRESS

COMMAND CODE

= MASTER-TO-SLAVE

= SLAVE-TO-MASTER

Figure 47. Send Byte Protocol

7-BIT SLAVE

ADDRESS

COMMAND

CODE

DATA

BYTE

= MASTER-TO-SLAVE

= SLAVE-TO-MASTER

Figure 48. Write Byte Protocol

DATA

BYTE

HIGH

COMMAND

CODE

DATA

BYTE

LOW

= MASTER-TO-SLAVE

= SLAVE-TO-MASTER

Figure 49. Write Word Protocol

DATA BYTE

COMMAND

CODE

= MASTER-TO-SLAVE

= SLAVE-TO-MASTER

Figure 50. Read Byte Protocol

DATA BYTE LOW

DATA BYTE HIGH

COMMAND

CODE

= MASTER-TO-SLAVE

= SLAVE-TO-MASTER

Figure 51. Read Word Protocol

DATA BYTE 1

...

DATA BYTE N

7-BIT SLAVE

ADDRESS

BYTE

COUNT = N

COMMAND

CODE

= MASTER-TO-SLAVE

= SLAVE-TO-MASTER

Figure 52. Block Write Protocol

COMMAND

CODE

DATA

BYTE 1

...

DATA

BYTE N

BYTE

COUNT = N

= MASTER-TO-SLAVE

= SLAVE-TO-MASTER

Figure 53. Block Read Protocol

Clock Generation and Stretching

The ADP1046A is always a slave in the overall system; therefore,

the device never needs to generate the clock, which is done by

the master device in the system. However, the I2C slave device is

capable of clock stretching to place the master in a wait state. By

stretching the SCL signal during the low period, the slave device

communicates to the master device that it is not ready and that

the master device must wait.

Conditions where the I2C slave device stretches the SCL line low

include the following:

•

The master device is transmitting at a higher baud rate

than the slave device.

•

The receive FIFO buffer of the slave device is full and must

be read before continuing. This prevents a data overflow

condition.

•

The slave device is not ready to send data that the master

has requested.

Note that the slave device can stretch the SCL line only during

the low period. Also, whereas the I2C specification allows indefinite

stretching of the SCL line, the ADP1046A limits the maximum

time that the SCL line can be stretched, or held low. For more

information about the maximum time, see the Timeout

Condition section.

Start and Stop Conditions

Start and stop conditions involve serial data transitions while the

serial clock is at a logic high level. The I2C slave device monitors

the SDA and SCL lines to detect the start and stop conditions

and transition its internal state machine accordingly. Typical

start and stop conditions are shown in Figure 54.

SCL

SDA

START

STOP

Figure 54. Start and Stop Transitions

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