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ADP1046AACPZ-R7 数据表(PDF) 76 Page - Analog Devices

部件名 ADP1046AACPZ-R7
功能描述  Digital Controller for Isolated Power Supply Applications
PDF  88 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP1046AACPZ-R7 数据表(HTML) 76 Page - Analog Devices

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ADP1046A
Data Sheet
Rev. 0 | Page 76 of 88
Bits
Bit Name
R/W
Description
2
t
3 sign
R/W
0 = positive sign. Increase of balance control modulation moves t
3 right.
1 = negative sign. Increase of balance control modulation moves t
3 left.
1
Modulate enable, t
4
R/W
Setting this bit enables modulation from balance control on the OUTB falling edge, t
4. It is
recommended that volt-second balance not be enabled on edges that are between 0 ns and
640 ns of the switching period.
0
t
4 sign
R/W
0 = positive sign. Increase of balance control modulation moves t
4 right.
1 = negative sign. Increase of balance control modulation moves t
4 left.
Table 111. Register 0x77—Volt-Second Balance Settings (OUTC and OUTD Pins)
Bits
Bit Name
R/W
Description
7
Modulate enable, t
5
R/W
Setting this bit enables modulation from balance control on the OUTC rising edge, t
5. It is
recommended that volt-second balance not be enabled on edges that are between 0 ns and
640 ns of the switching period.
6
t
5 sign
R/W
0 = positive sign. Increase of balance control modulation moves t
5 right.
1 = negative sign. Increase of balance control modulation moves t
5 left.
5
Modulate enable, t
6
R/W
Setting this bit enables modulation from balance control on the OUTC falling edge, t
6. It is
recommended that volt-second balance not be enabled on edges that are between 0 ns and
640 ns of the switching period.
4
t
6 sign
R/W
0 = positive sign. Increase of balance control modulation moves t
6 right.
1 = negative sign. Increase of balance control modulation moves t
6 left.
3
Modulate enable, t
7
R/W
Setting this bit enables modulation from balance control on the OUTD rising edge, t
7. It is
recommended that volt-second balance not be enabled on edges that are between 0 ns and
640 ns of the switching period.
2
t
7 sign
R/W
0 = positive sign. Increase of balance control modulation moves t
7 right.
1 = negative sign. Increase of balance control modulation moves t
7 left.
1
Modulate enable, t
8
R/W
Setting this bit enables modulation from balance control on the OUTD falling edge, t
8. It is
recommended that volt-second balance not be enabled on edges that are between 0 ns and
640 ns of the switching period.
0
t
8 sign
R/W
0 = positive sign. Increase of balance control modulation moves t
8 right.
1 = negative sign. Increase of balance control modulation moves t
8 left.
Table 112. Register 0x78—Volt-Second Balance Settings (SR1 and SR2 Pins)
Bits
Bit Name
R/W
Description
7
Modulate enable, t
9
R/W
Setting this bit enables modulation from balance control on the SR1 rising edge, t
9. It is
recommended that volt-second balance not be enabled on edges that are between 0 ns and
640 ns of the switching period.
6
t
9 sign
R/W
0 = positive sign. Increase of balance control modulation moves t
9 right.
1 = negative sign. Increase of balance control modulation moves t
9 left.
5
Modulate enable, t
10
R/W
Setting this bit enables modulation from balance control on the SR1 falling edge, t
10. It is
recommended that volt-second balance not be enabled on edges that are between 0 ns and
640 ns of the switching period.
4
t
10 sign
R/W
0 = positive sign. Increase of balance control modulation moves t
10 right.
1 = negative sign. Increase of balance control modulation moves t
10 left.
3
Modulate enable, t
11
R/W
Setting this bit enables modulation from balance control on the SR2 rising edge, t
11. It is
recommended that volt-second balance not be enabled on edges that are between 0 ns and
640 ns of the switching period.
2
t
11 sign
R/W
0 = positive sign. Increase of balance control modulation moves t
11 right.
1 = negative sign. Increase of balance control modulation moves t
11 left.
1
Modulate enable, t
12
R/W
Setting this bit enables modulation from balance control on the SR2 falling edge, t
12. It is
recommended that volt-second balance not be enabled on edges that are between 0 ns and
640 ns of the switching period.
0
t
12 sign
R/W
0 = positive sign. Increase of balance control modulation moves t
12 right.
1 = negative sign. Increase of balance control modulation moves t
12 left.



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