ADP1046AACPZ-R7 datasheet(18/88 Pages) AD

18 / 88 page

ADP1046A

Data Sheet

Rev. 0 | Page 18 of 88

To transfer the z-domain value to the s-domain, plug the follow-

ing bilinear transformation equation into the H(z) equation:

z(s)

−

The digital filter introduces an extra phase delay element into

the control loop. The digital filter circuit sends the duty cycle

information to the PWM circuit at the beginning of each switch-

ing cycle (unlike an analog controller, which makes decisions on

the duty cycle information continuously). Therefore, the extra

phase delay for phase margin, Φ, introduced by the filter block is

Φ = 360 × (fC/fSW)

where:

fC is the crossover frequency.

fSW is the switching frequency.

At one-tenth the switching frequency, the phase delay is 36°.

The GUI incorporates this phase delay into its calculations.

Note that the GUI does not account for other delays such as

gate driver and propagation delays.

Two sets of registers allow for two distinct filter responses.

The main filter, called the normal mode filter, is controlled by

programming Register 0x60 to Register 0x63. The light load

mode filter is controlled by programming Register 0x64 to

only when the output current measured on CS2± is below the

load current threshold (programmed using Register 0x3B[2:0]).

The Analog Devices software GUI allows the user to program the

light load mode filter in the same manner as the normal mode

filter. It is recommended that the GUI be used for this purpose.

In addition, during the soft start process, a soft start filter can

be used in combination with the normal mode filter and the

light load mode filter. The soft start filter is programmed using

Soft Start section.

Filter Transitions

To avoid output voltage glitches and provide a seamless

transition from one filter to another, the ADP1046A supports

programmable filter transitions. This feature allows a gradual

transition from one filter to another. Filter transitions are

programmed using Register 0x7A[2:0].

PWM AND SYNCHRONOUS RECTIFIER OUTPUTS

(OUTA, OUTB, OUTC, OUTD, OUTAUX, SR1, SR2)

The PWM and SR outputs are used for control of the primary

side drivers and the synchronous rectifier drivers. These outputs

can be used for several control topologies such as full-bridge,

phase-shifted ZVS configurations and interleaved, two switch

forward converter configurations. Delays between rising and

falling edges can be individually programmed. Special care

must be taken to avoid shoot-through and cross-conduction.

It is recommended that the Analog Devices software GUI be

used to program these outputs. Figure 21 shows an example

configuration to drive a full-bridge, phase-shifted topology

with synchronous rectification.

ISOLATOR

DRIVER

OUTA

OUTB

OUTC

OUTD

SR1

SR2

VIN

OUTA

OUTD

OUTC

OUTB

SR1

SR2

Figure 21. PWM Pin Assignment for Full-Bridge, Phase-Shifted Topology

with Synchronous Rectification

The PWM and SR outputs are all synchronized with each

other. Therefore, when reprogramming more than one of these

outputs, it is important to first update all the registers and then

latch the information into the ADP1046A at the same time. During

reprogramming, the outputs are temporarily disabled. A special

instruction is sent to the ADP1046A to ensure that new timing

information is programmed simultaneously. This is done by

setting Bit 1 in Register 0x7F. It is recommended that PWM

outputs be disabled when not in use.

OUTAUX is an additional PWM output pin. OUTAUX allows

an extra PWM signal to be generated at a different frequency

from the other six PWM outputs. This signal can be used to

drive an extra power converter stage, such as a buck controller

located in front of a full-bridge converter. OUTAUX can also

be used as a clock reference signal.

For more information about the various programmable switching

frequencies and PWM timings, see the PWM and Synchronous

Rectifier Timing Registers section (Register 0x3F to Register 0x5C).

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