ADP1046AACPZ-R7 datasheet(77/88 Pages) AD

77 / 88 page

Data Sheet

ADP1046A

Rev. 0 | Page 77 of 88

Table 113. Register 0x79—SR Delay Compensation

Bits

Bit Name

R/W

Description

[7:6]

Reserved

R/W

Reserved.

[5:0]

SR driver delay

R/W

These bits specify the 6-bit representation of the SR delay in steps of 5 ns.

000000 = 0 ns.

111111 = 63 ns × 5 ns = 315 ns.

Table 114. Register 0x7A—Filter Transitions

Bits

Bit Name

R/W

Description

[7:6]

Reserved

R/W

Reserved.

[5:3]

HF ADC configuration

R/W

Set these bits to 001 at all times for proper operation.

Enable soft transition

R/W

Setting this bit enables a soft transition between filter settings to minimize output transients.

All four parameters of each filter are linearly transitioned to the new value.

[1:0]

Transition speed

R/W

These bits set the transition speed from one filter to another. The filter changes in 32 steps;

each step is applied at the multiple of switching cycles (t

SW) specified by these bits.

Bit 1

Bit 0

Speed (t

SW = One Switching Cycle)

32 t

SW (total transition time = 32 × 32 tSW = 1024 × tSW)

8 t

SW (total transition time = 8 × 32 tSW = 256 × tSW)

2 t

SW (total transition time = 64 × tSW)

1 t

SW (total transition time = 32 × tSW)

Table 115. Register 0x7B—PGOOD1 Flag Masking

Bits

Bit Name

R/W

Description

Soft start flag

R/W

If this bit is set to 1, the soft start flag is ignored by PGOOD1. This bit must be set to 0 to enable

proper PGOOD1 debounce timing after the end of the soft start ramp.

CS1 fast OCP

R/W

If this bit is set to 1, the CS1 fast OCP flag is ignored by PGOOD1.

CS1 accurate OCP

R/W

If this bit is set to 1, the CS1 accurate OCP flag is ignored by PGOOD1.

CS2 accurate OCP

R/W

If this bit is set to 1, the CS2 accurate OCP flag is ignored by PGOOD1.

UVP

R/W

If this bit is set to 1, the UVP flag is ignored by PGOOD1.

Local OVP (fast and

accurate)

R/W

If this bit is set to 1, the local OVP flag is ignored by PGOOD1.

Load OVP

R/W

If this bit is set to 1, the load OVP flag is ignored by PGOOD1.

OrFET

R/W

If this bit is set to 1, the OrFET flag is ignored by PGOOD1.

Table 116. Register 0x7C—PGOOD2 Flag Masking

Bits

Bit Name

R/W

Description

Soft start flag

R/W

If this bit is set to 1, the soft start flag is ignored by PGOOD2. This bit must be set to 0 to enable

proper PGOOD2 debounce timing after the end of the soft start ramp.

CS1 fast OCP

R/W

If this bit is set to 1, the CS1 fast OCP flag is ignored by PGOOD2.

CS1 accurate OCP

R/W

If this bit is set to 1, the CS1 accurate OCP flag is ignored by PGOOD2.

CS2 accurate OCP

R/W

If this bit is set to 1, the CS2 accurate OCP flag is ignored by PGOOD2.

UVP

R/W

If this bit is set to 1, the UVP flag is ignored by PGOOD2.

Local OVP (fast and

accurate)

R/W

If this bit is set to 1, the local OVP flag is ignored by PGOOD2.

Load OVP

R/W

If this bit is set to 1, the load OVP flag is ignored by PGOOD2.

OrFET

R/W

If this bit is set to 1, the OrFET flag is ignored by PGOOD2.

ADP1046AACPZ-R7 数据表(PDF) 77 Page - Analog Devices

ADP1046AACPZ-R7 数据表(HTML) 77 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

数据表下载

链接网址

ADP1046AACPZ-R7 数据表(PDF) 77 Page - Analog Devices

ADP1046AACPZ-R7 数据表(HTML) 77 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

数据表 下载

链接网址

数据表下载