ADP1046AACPZ-R7 datasheet(82/88 Pages) AD

82 / 88 page

ADP1046A

Data Sheet

Rev. 0 | Page 82 of 88

RESONANT MODE OPERATION

The ADP1046A supports control of a resonant converter.

Resonant converters are an alternative to traditional fixed

frequency converters. They offer high switching frequency,

small size, and high efficiency. Figure 59 illustrates a widely

used series resonant converter.

SR2

SR1

Figure 59. Series Resonant Converter

RESONANT MODE ENABLE

To enable the ADP1046A to control a resonant switching con-

verter, Register 0x40 must be set to a value of 0x3F. In resonant

mode, the PWM outputs have a fixed duty cycle with variable

frequency.

PWM TIMING IN RESONANT MODE

With variable frequency control, OUTA and OUTB can only be

high during the first half of the switching cycle (tA to tB), whereas

OUTC and OUTD can only be high during the second half of

the switching cycle (tB to tC), as shown in Figure 60. The

frequency resolution of the control law is in steps of 10 ns.

PWM1 (OUTA)

PWM2 (OUTB)

PWM3 (OUTC)

PWM4 (OUTD)

Δt

tPERIOD

Figure 60. OUTA, OUTB, OUTC, and OUTD PWM Timing Diagram

in Resonant Mode

SYNCHRONOUS RECTIFICATION IN RESONANT

MODE

Control of the synchronous rectifiers in a resonant controller is

a complicated issue. The ADP1046A ACSNS comparator can be

used to control the SR signals. In resonant mode operation, the

SR1 output is driven by the rising edge of the ACSNS comparator,

and the SR2 output is driven by the falling edge of the comparator,

as shown in Figure 61.

VDS (SR2)

ACSNS

SYNC RECT 1 (SR1)

SYNC RECT 2 (SR2)

Δt

Figure 61. SR1 and SR2 PWM Timing Diagram in Resonant Mode

Following is an example of how the ADP1046A can be used in a

series resonant topology and also achieve control of the synchro-

nous rectifiers. The VDS voltage of SR2 (see Figure 61) can be

used to control the SR signals. The ACSNS pin is connected to

the divided-down SR2 VDS voltage. This provides the timing

information for both synchronous rectifiers (see Figure 62).

SR2

SR1

ACSNS

Figure 62. Resonant Synchronous Rectifier Control Circuit

After the timing information is obtained, SR1 is driven by the

rising edge of the ACSNS comparator, and SR2 is driven by the

falling edge of the comparator, as shown in Figure 61. In this

way, it is possible to achieve synchronous rectification. Turn-on

and turn-off delays can be programmed for the SR1 and SR2

signals individually.

This example is not the only way to control the SR signals. If the

user has another method to control the SR signals, this method

can be used to connect to the ACSNS input instead of the VDS

voltage of SR2.

When the ADP1046A is used to control a resonant converter, it

is recommended that SR soft start be disabled during soft start

of the device (set Register 0x0F[7] = 1).

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